{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,3]],"date-time":"2024-09-03T21:06:06Z","timestamp":1725397566854},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,7]]},"DOI":"10.1109\/nanoarch.2017.8053707","type":"proceedings-article","created":{"date-parts":[[2017,10,2]],"date-time":"2017-10-02T20:24:16Z","timestamp":1506975856000},"page":"119-124","source":"Crossref","is-referenced-by-count":1,"title":["Mixing circuit based on neural associative memories and nanoelectronic 1S1R cells"],"prefix":"10.1109","author":[{"given":"Arne","family":"Heittmann","sequence":"first","affiliation":[]},{"given":"Tobias G.","family":"Noll","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2014.6865157"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/SNW.2016.7578035"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1063\/1.367317"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2765491.2765509"},{"journal-title":"Self-Checking and Fault-Tolerant Digital Design","year":"2000","author":"parag","key":"ref14"},{"journal-title":"ITRS Roadmap","year":"0","key":"ref4"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1002\/adma.200900375"},{"key":"ref6","first-page":"94","article-title":"GMS: Generic memristive structure for nonvolatile FPGAs","author":"gaillardon","year":"2012","journal-title":"VLSI-SoC 2012"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2015.7168889"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2016.7538936"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/NANOARCH.2015.7180599"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1007\/BF00337019"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1016\/j.ipl.2005.05.021"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JEDS.2016.2594190"}],"event":{"name":"2017 IEEE\/ACM International Symposium on Nanoscale Architectures (NANOARCH)","start":{"date-parts":[[2017,7,25]]},"location":"Newport, RI, USA","end":{"date-parts":[[2017,7,26]]}},"container-title":["2017 IEEE\/ACM International Symposium on Nanoscale Architectures (NANOARCH)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8048800\/8053702\/08053707.pdf?arnumber=8053707","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,12,13]],"date-time":"2017-12-13T20:53:21Z","timestamp":1513198401000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8053707\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,7]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/nanoarch.2017.8053707","relation":{},"subject":[],"published":{"date-parts":[[2017,7]]}}}