{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T19:38:17Z","timestamp":1729625897402,"version":"3.28.0"},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,7]]},"DOI":"10.1109\/nanoarch.2017.8053713","type":"proceedings-article","created":{"date-parts":[[2017,10,2]],"date-time":"2017-10-02T20:24:16Z","timestamp":1506975856000},"page":"95-96","source":"Crossref","is-referenced-by-count":3,"title":["Reconfigurable processing in memory architecture based on spin orbit torque"],"prefix":"10.1109","author":[{"given":"Liang","family":"Chang","sequence":"first","affiliation":[]},{"given":"Zhaohao","family":"Wang","sequence":"additional","affiliation":[]},{"given":"Youguang","family":"Zhang","sequence":"additional","affiliation":[]},{"given":"Weisheng","family":"Zhao","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750385"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2015.7062931"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/2370816.2370865"},{"key":"ref6","doi-asserted-by":"crossref","DOI":"10.1126\/science.1218197","article-title":"Spin-Torque Switching with the Giant Spin Hall Effect of Tantalum","volume":"336","author":"liu","year":"2012","journal-title":"Science"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1088\/0022-3727\/48\/6\/065001"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2389260"},{"key":"ref7","first-page":"73","article-title":"Evaluation of Spin-Hall-assisted STT-MRAM for Cache Replacement","author":"chang","year":"0","journal-title":"IEEE\/ACM NANOARCH"},{"key":"ref2","first-page":"27","article-title":"PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory","volume":"44","author":"chi","year":"2016","journal-title":"IEEE\/ACM ISCA"},{"journal-title":"STMicroelectronics","article-title":"CMOS40 Design Rule Manual","year":"2012","key":"ref9"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2011.89"}],"event":{"name":"2017 IEEE\/ACM International Symposium on Nanoscale Architectures (NANOARCH)","start":{"date-parts":[[2017,7,25]]},"location":"Newport, RI, USA","end":{"date-parts":[[2017,7,26]]}},"container-title":["2017 IEEE\/ACM International Symposium on Nanoscale Architectures (NANOARCH)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8048800\/8053702\/08053713.pdf?arnumber=8053713","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,10,4]],"date-time":"2019-10-04T05:13:56Z","timestamp":1570166036000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8053713\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,7]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/nanoarch.2017.8053713","relation":{},"subject":[],"published":{"date-parts":[[2017,7]]}}}