{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T11:55:18Z","timestamp":1725796518935},"reference-count":37,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,7]]},"DOI":"10.1109\/nanoarch.2017.8053733","type":"proceedings-article","created":{"date-parts":[[2017,10,2]],"date-time":"2017-10-02T16:24:16Z","timestamp":1506961456000},"page":"55-60","source":"Crossref","is-referenced-by-count":17,"title":["Architecture, design and technology guidelines for crosspoint memories"],"prefix":"10.1109","author":[{"given":"A.","family":"Levisse","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"p.","family":"Royer","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"B.","family":"Giraud","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.P.","family":"Noel","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Moreau","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.M.","family":"Portal","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/IITC-AMC.2016.7507649"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2016.7838348"},{"key":"ref31","article-title":"Calculation of &#x2018;Elmore&#x2019; delay for RC ladder networks","author":"lamdan","year":"2010","journal-title":"Proceedings of the Institution of Electrical Engineers"},{"key":"ref30","article-title":"A 128Gb MLC NAND-Flash device using 16nm planar cell","author":"helmet","year":"2014","journal-title":"ISSCC"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2017.7870432"},{"key":"ref36","article-title":"An 8Gb 12Gb\/s\/pin GDDR5X DRAM for cost-effective highperformance applications","author":"brox","year":"2017","journal-title":"ISSCC"},{"key":"ref35","article-title":"32nm 3-bit 32Gb NAND Flash Memory with DPT (double patterning technology) process for mass production","author":"park","year":"2010","journal-title":"VLSIT"},{"key":"ref34","article-title":"A 19nm 112.8mm2 64Gb multi-level flash memory with 400Mb\/s\/pin 1.8V Toggle Mode interface","author":"shibata","year":"2012","journal-title":"ISSCC"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.7873\/DATE2014.282"},{"key":"ref11","article-title":"Fully CMOS compatible 3D vertical RRAM with self-aligned self-selective cell enabling sub-5nm scaling","author":"xu","year":"2016","journal-title":"IEEE Symp VLSI Technol"},{"key":"ref12","article-title":"A 130.7-mm 2-Layer 32-Gb ReRAM Memory Device in 24-nm Technology","author":"liu","year":"2014","journal-title":"JSSC"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2215121"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JEDS.2016.2594190"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2014.6849358"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2012.6241805"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/LASCAS.2017.7948104"},{"key":"ref18","article-title":"Crossbar RRAM Arrays: Selector Device Requirements During Write Operation","author":"kim","year":"2014","journal-title":"TED"},{"key":"ref19","article-title":"Crossbar RRAM Arrays: Selector Device Requirements During Read Operation","author":"zhou","year":"2014","journal-title":"TED"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2014.6865157"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2352293"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/NVMTS.2015.7457426"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2013.6724554"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2010.2070050"},{"year":"0","key":"ref29"},{"key":"ref5","article-title":"The bleak future of NAND flash memory","author":"grupp","year":"2012","journal-title":"FAST"},{"key":"ref8","article-title":"Metal-Oxide RRAM","author":"wong","year":"2012","journal-title":"Proc of the IEEE"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2016.2590142"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ICICDT.2016.7542072"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2014.7046995"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2016.7428079"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2013.2246791"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2012.6479146"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2015.7168603"},{"key":"ref24","article-title":"Highly Compact 1T-1R Architecture (4F2 Footprint) Involving Fully CMOS Compatible Vertical GAA Nano-Pillar Transistors and Oxide-Based RRAM Cells Exhibiting Excellent NVM Properties and Ultra-Low Power Operation","author":"wang","year":"2012","journal-title":"IEDM"},{"key":"ref23","article-title":"Three-Dimensional 4F2 ReRAM With Vertical BJT Driver by CMOS Logic Compatible Process","author":"wang","year":"2011","journal-title":"IEDM"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2010.2062187"},{"key":"ref25","article-title":"Capacitor based SneakPath compensation circuit for transistor-less ReRAM architectures","author":"levisse","year":"2016","journal-title":"Nanoarch"}],"event":{"name":"2017 IEEE\/ACM International Symposium on Nanoscale Architectures (NANOARCH)","start":{"date-parts":[[2017,7,25]]},"location":"Newport, RI, USA","end":{"date-parts":[[2017,7,26]]}},"container-title":["2017 IEEE\/ACM International Symposium on Nanoscale Architectures (NANOARCH)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8048800\/8053702\/08053733.pdf?arnumber=8053733","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,10,27]],"date-time":"2017-10-27T17:31:08Z","timestamp":1509125468000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8053733\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,7]]},"references-count":37,"URL":"https:\/\/doi.org\/10.1109\/nanoarch.2017.8053733","relation":{},"subject":[],"published":{"date-parts":[[2017,7]]}}}