{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,21]],"date-time":"2025-06-21T11:02:30Z","timestamp":1750503750574,"version":"3.28.0"},"reference-count":21,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,10,1]],"date-time":"2021-10-01T00:00:00Z","timestamp":1633046400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,10,1]],"date-time":"2021-10-01T00:00:00Z","timestamp":1633046400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,10,1]],"date-time":"2021-10-01T00:00:00Z","timestamp":1633046400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,10]]},"DOI":"10.1109\/nas51552.2021.9605440","type":"proceedings-article","created":{"date-parts":[[2021,11,22]],"date-time":"2021-11-22T21:12:15Z","timestamp":1637615535000},"page":"1-8","source":"Crossref","is-referenced-by-count":2,"title":["Cache Compression with Efficient in-SRAM Data Comparison"],"prefix":"10.1109","author":[{"given":"Xiaowei","family":"Wang","sequence":"first","affiliation":[]},{"given":"Charles","family":"Augustine","sequence":"additional","affiliation":[]},{"given":"Eriko","family":"Nurvitadhi","sequence":"additional","affiliation":[]},{"given":"Ravi","family":"Iyer","sequence":"additional","affiliation":[]},{"given":"Li","family":"Zhao","sequence":"additional","affiliation":[]},{"given":"Reetuparna","family":"Das","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","first-page":"1","article-title":"Simpoint 3.0: Faster and more flexible program phase analysis","volume":"7","author":"hamerly","year":"2005","journal-title":"Journal of Instruction Level Parallelism"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/1064978.1065034"},{"key":"ref12","first-page":"91","article-title":"Sniper: Scalable and accurate parallel multi-core simulation","author":"heirman","year":"2012","journal-title":"8th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES-2012)"},{"article-title":"Frequent pattern compression: A significance-based compression scheme for l2 caches","year":"2004","author":"alameldeen","key":"ref13"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2002.1003572"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/1542275.1542288"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2020989"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540715"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.41"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/2976740"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.21"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2258815"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2515510"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00040"},{"key":"ref8","doi-asserted-by":"crossref","first-page":"377","DOI":"10.1145\/2370816.2370870","article-title":"Base-Delta-Immediate Compression: Practical Data Compression for On-Chip Caches","author":"gennady pekhimenko","year":"2012","journal-title":"In International Conference on Parallel Architectures and Compilation Techniques (PACT)"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/3307650.3322257"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/3373376.3378518"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3123986"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/2597652.2597655"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2014.6853231"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/3297858.3304006"}],"event":{"name":"2021 IEEE International Conference on Networking, Architecture and Storage (NAS)","start":{"date-parts":[[2021,10,24]]},"location":"Riverside, CA, USA","end":{"date-parts":[[2021,10,26]]}},"container-title":["2021 IEEE International Conference on Networking, Architecture and Storage (NAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9605358\/9605359\/09605440.pdf?arnumber=9605440","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T16:51:25Z","timestamp":1652201485000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9605440\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,10]]},"references-count":21,"URL":"https:\/\/doi.org\/10.1109\/nas51552.2021.9605440","relation":{},"subject":[],"published":{"date-parts":[[2021,10]]}}}