{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T09:37:45Z","timestamp":1725701865723},"reference-count":19,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,10,1]],"date-time":"2021-10-01T00:00:00Z","timestamp":1633046400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,10,1]],"date-time":"2021-10-01T00:00:00Z","timestamp":1633046400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,10,1]],"date-time":"2021-10-01T00:00:00Z","timestamp":1633046400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,10]]},"DOI":"10.1109\/nas51552.2021.9605470","type":"proceedings-article","created":{"date-parts":[[2021,11,22]],"date-time":"2021-11-22T16:12:15Z","timestamp":1637597535000},"page":"1-6","source":"Crossref","is-referenced-by-count":2,"title":["PLMC: A Predictable Tail Latency Mode Coordinator for Shared NVMe SSD with Multiple Hosts"],"prefix":"10.1109","author":[{"given":"Tanaya","family":"Roy","sequence":"first","affiliation":[],"role":[{"role":"author","vocab":"crossref"}]},{"given":"Jit","family":"Gupta","sequence":"additional","affiliation":[],"role":[{"role":"author","vocab":"crossref"}]},{"given":"Krishna","family":"Kant","sequence":"additional","affiliation":[],"role":[{"role":"author","vocab":"crossref"}]},{"given":"Amitangshu","family":"Pal","sequence":"additional","affiliation":[],"role":[{"role":"author","vocab":"crossref"}]},{"given":"Dave","family":"Minturn","sequence":"additional","affiliation":[],"role":[{"role":"author","vocab":"crossref"}]},{"given":"Arash","family":"Tavakkol","sequence":"additional","affiliation":[],"role":[{"role":"author","vocab":"crossref"}]}],"member":"263","reference":[{"year":"2019","key":"ref10","article-title":"Nvm express base specification, rev 1.4"},{"key":"ref11","first-page":"49","article-title":"Mqsim: A framework for enabling realistic studies of modern multi-queue SSD devices","author":"tavakkol","year":"2018","journal-title":"USENIX FAST"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/1027794.1027801"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1007\/978-94-007-5146-0_2"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-51735-3_1"},{"key":"ref15","first-page":"799","article-title":"Alleviating garbage collection interference through spatial separation in all flash arrays","author":"kim","year":"2019","journal-title":"USENIX ATC"},{"key":"ref16","article-title":"Under the hood with nvme over fabrics","author":"minturn","year":"2015","journal-title":"Ethernet Storage Forum"},{"year":"0","key":"ref17","article-title":"Systor&#x2019;17 fujitsu laboratory traces"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.17485\/ijst\/2014\/v7i6.14"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/3078468.3078483"},{"key":"ref4","article-title":"Nvm express","author":"huffman","year":"2012","journal-title":"revision 1 0 c Intel Corporation"},{"article-title":"An introduction to nvme","year":"0","author":"strass","key":"ref3"},{"key":"ref6","doi-asserted-by":"crossref","first-page":"107","DOI":"10.1145\/3297858.3304005","article-title":"Parties: Qos-aware resource partitioning for multiple interactive services","author":"chen","year":"2019","journal-title":"Proceedings of the fourth international conference on Architectural support for programming languages and operating systems - AS"},{"year":"2020","key":"ref5"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1323293.1294281"},{"key":"ref7","first-page":"329","article-title":"Bobtail: Avoiding long tails in the cloud","author":"xu","year":"2013","journal-title":"USENIX NSDI"},{"key":"ref2","article-title":"Nvm express and the pci express ssd revolution","author":"cobb","year":"2012","journal-title":"Intel Developer Forum"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/978-94-007-5146-0"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/2408776.2408794"}],"event":{"name":"2021 IEEE International Conference on Networking, Architecture and Storage (NAS)","start":{"date-parts":[[2021,10,24]]},"location":"Riverside, CA, USA","end":{"date-parts":[[2021,10,26]]}},"container-title":["2021 IEEE International Conference on Networking, Architecture and Storage (NAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9605358\/9605359\/09605470.pdf?arnumber=9605470","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T12:51:25Z","timestamp":1652187085000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9605470\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,10]]},"references-count":19,"URL":"https:\/\/doi.org\/10.1109\/nas51552.2021.9605470","relation":{},"subject":[],"published":{"date-parts":[[2021,10]]}}}