{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,4]],"date-time":"2025-12-04T09:57:18Z","timestamp":1764842238290},"reference-count":10,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,3,1]],"date-time":"2019-03-01T00:00:00Z","timestamp":1551398400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,3,1]],"date-time":"2019-03-01T00:00:00Z","timestamp":1551398400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,3,1]],"date-time":"2019-03-01T00:00:00Z","timestamp":1551398400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,3]]},"DOI":"10.1109\/ner.2019.8717135","type":"proceedings-article","created":{"date-parts":[[2019,5,20]],"date-time":"2019-05-20T22:46:49Z","timestamp":1558392409000},"page":"791-794","source":"Crossref","is-referenced-by-count":5,"title":["NeuralCLIP: A Modular FPGA-Based Neural Interface for Closed-Loop Operation"],"prefix":"10.1109","author":[{"given":"Vaishnavi","family":"Ranganathan","sequence":"first","affiliation":[]},{"given":"Jared","family":"Nakahara","sequence":"additional","affiliation":[]},{"given":"Soshi","family":"Samejima","sequence":"additional","affiliation":[]},{"given":"Nicholas","family":"Tolley","sequence":"additional","affiliation":[]},{"given":"Abed","family":"Khorasani","sequence":"additional","affiliation":[]},{"given":"Chet T.","family":"Moritz","sequence":"additional","affiliation":[]},{"given":"Joshua R.","family":"Smith","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TBCAS.2016.2574362"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1007\/s11517-015-1430-4"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TNSRE.2017.2751579"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/WPT.2016.7498826"},{"key":"ref5","first-page":"1","article-title":"A 4.78mm2 fully-integrated neuromodulation soc combining 64 acquisition channels with digital compression and simultaneous dual stimulation","author":"yeager","year":"2014","journal-title":"IEEE VLSI Des"},{"key":"ref8","first-page":"284","article-title":"A brainspine interface alleviating gait deficits after spinal cord injury in primates","author":"capogrosso","year":"0","journal-title":"Nature"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2284346"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.811979"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.3389\/fnins.2014.00021"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1038\/35053191"}],"event":{"name":"2019 9th International IEEE\/EMBS Conference on Neural Engineering (NER)","start":{"date-parts":[[2019,3,20]]},"location":"San Francisco, CA, USA","end":{"date-parts":[[2019,3,23]]}},"container-title":["2019 9th International IEEE\/EMBS Conference on Neural Engineering (NER)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8712471\/8716881\/08717135.pdf?arnumber=8717135","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,18]],"date-time":"2022-07-18T14:44:46Z","timestamp":1658155486000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8717135\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,3]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/ner.2019.8717135","relation":{},"subject":[],"published":{"date-parts":[[2019,3]]}}}