{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T10:42:08Z","timestamp":1730284928557,"version":"3.28.0"},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,12]]},"DOI":"10.1109\/nesea.2011.6144953","type":"proceedings-article","created":{"date-parts":[[2012,2,3]],"date-time":"2012-02-03T20:42:22Z","timestamp":1328301742000},"page":"1-6","source":"Crossref","is-referenced-by-count":3,"title":["New structure for adder with improved speed, area and power"],"prefix":"10.1109","author":[{"given":"Karami H.","family":"Fatemeh","sequence":"first","affiliation":[]},{"given":"Ali K.","family":"Horestani","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/12.2261"},{"key":"ref11","first-page":"434","article-title":"The fastest carry lookahead adder","author":"pai","year":"2004","journal-title":"Proceedings of the Second IEEE International Workshop on Electronic Design Test and Applications"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ACSSC.2001.987705"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ACSSC.1990.523471"},{"key":"ref14","article-title":"Efficient Adders to Speedup Modular Multiplication for Cryptography","author":"gutub","year":"2008","journal-title":"Proc Int'l Workshop Signal Processing and Its Applications"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/EDM.2010.5568844"},{"article-title":"Logic And Computer Design Fundamentals–2nd Edition","year":"2001","author":"mano","key":"ref4"},{"key":"ref3","first-page":"322","article-title":"Delay-insensitive carry-lookahead adders","author":"cheng","year":"1997","journal-title":"vlsid"},{"journal-title":"Basic VLSI Design","year":"1994","author":"pucknell","key":"ref6"},{"key":"ref5","first-page":"898","volume":"34","author":"lim","year":"2001","journal-title":"Logic and Computer Design Fundamentals"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/82.539001"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/IRETELC.1962.5407919"},{"article-title":"Cell-Based VLSI Implementations of the Add One Carry Select Adder","year":"2011","author":"monteiro","key":"ref2"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCSE.2009.5228242"},{"article-title":"CMOS VLSI design: a circuits and systems perspective","year":"2010","author":"weste","key":"ref9"}],"event":{"name":"2011 IEEE 2nd International Conference on Networked Embedded Systems for Enterprise Applications (NESEA)","start":{"date-parts":[[2011,12,8]]},"location":"Perth, Australia","end":{"date-parts":[[2011,12,9]]}},"container-title":["2011 IEEE 2nd International Conference on Networked Embedded Systems for Enterprise Applications"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6139205\/6144929\/06144953.pdf?arnumber=6144953","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T15:03:27Z","timestamp":1490108607000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6144953\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,12]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/nesea.2011.6144953","relation":{},"subject":[],"published":{"date-parts":[[2011,12]]}}}