{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T22:09:13Z","timestamp":1729634953648,"version":"3.28.0"},"reference-count":8,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,6]]},"DOI":"10.1109\/newcas.2014.6934070","type":"proceedings-article","created":{"date-parts":[[2014,11,1]],"date-time":"2014-11-01T04:44:26Z","timestamp":1414817066000},"page":"413-416","source":"Crossref","is-referenced-by-count":0,"title":["The P\/DLL frequency synthesizer architecture: A native trade-off between stability and wideband frequency generation"],"prefix":"10.1109","author":[{"given":"Y.","family":"Deval","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"P-O. Lucas","family":"de Peslouan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"T.","family":"Taris","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"De Matos","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"D.","family":"Belot","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/4.890315"},{"key":"2","article-title":"Phase-locked loops","author":"best","year":"1984","journal-title":"Theory Design and Applications"},{"key":"1","first-page":"230","article-title":"La r\ufffdception synchrone","volume":"11","author":"de bellescize","year":"1932","journal-title":"L'Onde Electrique"},{"journal-title":"Device and Method for Generating A Signal of Parametrizable Frequency","year":"2012","author":"deval","key":"7"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/RME.2007.4401843"},{"key":"5","doi-asserted-by":"crossref","first-page":"23","DOI":"10.29292\/jics.v5i1.307","article-title":"Voltage controlled delay line with phase quadrature outputs for [0. 9-4]GHz factorial delay locked loop dedicated to zero-IF multi-standard local oscillator","author":"majek","year":"2010","journal-title":"Journal of Integrated Circuits and Systems"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/4.987085"},{"key":"8","first-page":"482","article-title":"A new frequency synthesizers stabilization method based on a mixed phase locked loop and delay locked loop architecture","author":"peslouan de lucas","year":"2010","journal-title":"IEEE Proceedings-of the International Symposium on Circuits and Systems (ISCAS 2010)"}],"event":{"name":"2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS)","start":{"date-parts":[[2014,6,22]]},"location":"Trois-Rivieres, QC, Canada","end":{"date-parts":[[2014,6,25]]}},"container-title":["2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6919808\/6933969\/06934070.pdf?arnumber=6934070","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,21]],"date-time":"2022-04-21T01:35:09Z","timestamp":1650504909000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6934070\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,6]]},"references-count":8,"URL":"https:\/\/doi.org\/10.1109\/newcas.2014.6934070","relation":{},"subject":[],"published":{"date-parts":[[2014,6]]}}}