{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T05:45:11Z","timestamp":1729662311196,"version":"3.28.0"},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,6]]},"DOI":"10.1109\/newcas.2015.7181999","type":"proceedings-article","created":{"date-parts":[[2015,8,13]],"date-time":"2015-08-13T12:22:41Z","timestamp":1439468561000},"page":"1-4","source":"Crossref","is-referenced-by-count":2,"title":["Low-power hybrid STT\/CMOS system-on-chip embedding non-volatile magnetic memory blocks"],"prefix":"10.1109","author":[{"given":"Christophe","family":"Layer","sequence":"first","affiliation":[]},{"given":"Kotb","family":"Jabeur","sequence":"additional","affiliation":[]},{"given":"Stephane","family":"Gros","sequence":"additional","affiliation":[]},{"given":"Laurent","family":"Becker","sequence":"additional","affiliation":[]},{"given":"Pierre","family":"Paoli","sequence":"additional","affiliation":[]},{"given":"Fabrice","family":"Bernard-Granger","sequence":"additional","affiliation":[]},{"given":"Virgile","family":"Javerliac","sequence":"additional","affiliation":[]},{"given":"Bernard","family":"Dieny","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1147\/rd.501.0025"},{"article-title":"OpenRISC 1000 Architecture Manual","year":"2012","author":"lampret","key":"ref11"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TIT.1977.1055714"},{"key":"ref13","doi-asserted-by":"crossref","first-page":"1098","DOI":"10.1109\/JRPROC.1952.273898","article-title":"A Methodfor the Construction of Minimum-Redundancy Codes","author":"huffman","year":"1952","journal-title":"Proc IRE"},{"key":"ref4","first-page":"74001","article-title":"Basic Principles of STT-MRAM Cell Operation in Memory Arrays","volume":"46","author":"khvalkovskiy","year":"2013","journal-title":"J Applied Physics"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2010.198"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1840845.1840931"},{"key":"ref5","first-page":"194","article-title":"Nonvolatile Logic-in-Memory Array Processor in 90nm MTJ\/MOS","author":"natsui","year":"2013","journal-title":"Proc IEEE ISSCC"},{"key":"ref8","article-title":"A Hybrid Magnetic\/CMOS PDK for the Design of Low-Power Logic Circuits","volume":"111","author":"di pendina","year":"0","journal-title":"J Appl Phys"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2013.6557176"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.42"},{"article-title":"The Problem of Power Consumption in Servers","year":"2009","author":"minas","key":"ref1"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1049\/el.2014.1083"}],"event":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","start":{"date-parts":[[2015,6,7]]},"location":"Grenoble, France","end":{"date-parts":[[2015,6,10]]}},"container-title":["2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7157844\/7181973\/07181999.pdf?arnumber=7181999","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,23]],"date-time":"2017-06-23T13:35:56Z","timestamp":1498224956000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7181999\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,6]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/newcas.2015.7181999","relation":{},"subject":[],"published":{"date-parts":[[2015,6]]}}}