{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T18:36:32Z","timestamp":1729622192649,"version":"3.28.0"},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,6]]},"DOI":"10.1109\/newcas.2017.8010155","type":"proceedings-article","created":{"date-parts":[[2017,8,14]],"date-time":"2017-08-14T16:31:11Z","timestamp":1502728271000},"page":"261-264","source":"Crossref","is-referenced-by-count":3,"title":["A 0.15 to 2.2 GHz all-digital delay-locked loop"],"prefix":"10.1109","author":[{"given":"Dongjun","family":"Park","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Geontae","family":"Park","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jongsun","family":"Kim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2015.2468911"},{"key":"ref3","first-page":"168","article-title":"A 1.2 V 30 nm 3.2 Gb\/s\/pin 4 Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme","volume":"48","author":"sohn","year":"2006","journal-title":"IEEE Trans Circuits Syst"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.5573\/JSTS.2016.16.4.520"},{"key":"ref6","doi-asserted-by":"crossref","first-page":"395","DOI":"10.1109\/TCSI.2014.2364103","article-title":"An all-digital delay-locked loop using an in-time phase maintenance scheme for low-jitter gigahertz operations","volume":"62","author":"wang","year":"2015","journal-title":"IEEE Trans Circuits Syst"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.889381"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.889381"},{"key":"ref12","first-page":"341","article-title":"A 0.1-1.5 GHz all-digital phase inversion delay-locked loop","author":"han","year":"2013","journal-title":"IEEE Asian Solid State Circuits Conference"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2010.2048379"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1049\/el.2015.2876"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2015.2456111"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/IPEC.2012.6522683"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"2186","DOI":"10.1109\/TCSI.2012.2188943","article-title":"Process variation tolerant all-digital 90° phase shift DLL for DDR3 interface","volume":"59","author":"kang","year":"2012","journal-title":"IEEE Trans Circuits Syst"}],"event":{"name":"2017 15th IEEE International New Circuits and Systems Conference (NEWCAS)","start":{"date-parts":[[2017,6,25]]},"location":"Strasbourg, France","end":{"date-parts":[[2017,6,28]]}},"container-title":["2017 15th IEEE International New Circuits and Systems Conference (NEWCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8001599\/8010082\/08010155.pdf?arnumber=8010155","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,10,2]],"date-time":"2019-10-02T07:47:17Z","timestamp":1570002437000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8010155\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,6]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/newcas.2017.8010155","relation":{},"subject":[],"published":{"date-parts":[[2017,6]]}}}