{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T20:15:53Z","timestamp":1725567353790},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,6]]},"DOI":"10.1109\/newcas.2018.8585494","type":"proceedings-article","created":{"date-parts":[[2019,1,18]],"date-time":"2019-01-18T21:00:57Z","timestamp":1547845257000},"page":"205-208","source":"Crossref","is-referenced-by-count":4,"title":["Utilizing Dynamic Partial Reconfiguration to Reduce the Cost of FPGA Debugging"],"prefix":"10.1109","author":[{"given":"Islam","family":"Ahmed","sequence":"first","affiliation":[]},{"given":"Ahmed","family":"Kamaleldin","sequence":"additional","affiliation":[]},{"given":"Hassan","family":"Mostafa","sequence":"additional","affiliation":[]},{"given":"Ahmed Nader","family":"Mohieldin","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"year":"2017","key":"ref4","article-title":"Certus Debug Suite"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2145694.2145720"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2012.6176481"},{"year":"2012","key":"ref6","article-title":"Quartus II Handbook Version 12.1 Volume 3: Verification"},{"year":"0","key":"ref11","article-title":"Partial Reconfiguration, User Guide UG909(v16.1)"},{"year":"2012","key":"ref5","article-title":"ChipScope Pro Software and Cores, User Guide UG029(v14.3)"},{"year":"0","key":"ref12","article-title":"ZC702 Evaluation Board, User Guide UG850(v1.5)"},{"key":"ref8","article-title":"Instrumenting Bitstreams for Debugging FPGA Circuits","author":"graham","year":"2001","journal-title":"Field-Programmable Custom Computing Machines"},{"key":"ref7","doi-asserted-by":"crossref","first-page":"483","DOI":"10.1007\/3-540-44687-7_50","article-title":"Using DesignLevel Scan to Improve FPGA Design Observability and Controllability for Functional Verification","author":"wheeler","year":"2001","journal-title":"Proceedings of the 11th International Conference on Field-Programmable Logic and Applications"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2014.29"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2009.5161224"},{"article-title":"Challenges of Design and Verification in the SoC Era","year":"2011","author":"foster","key":"ref1"}],"event":{"name":"2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)","start":{"date-parts":[[2018,6,24]]},"location":"Montreal, QC","end":{"date-parts":[[2018,6,27]]}},"container-title":["2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8572699\/8585422\/08585494.pdf?arnumber=8585494","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,8,24]],"date-time":"2020-08-24T00:21:44Z","timestamp":1598228504000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8585494\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,6]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/newcas.2018.8585494","relation":{},"subject":[],"published":{"date-parts":[[2018,6]]}}}