{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,24]],"date-time":"2026-02-24T05:32:19Z","timestamp":1771911139643,"version":"3.50.1"},"reference-count":9,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,6,13]],"date-time":"2021-06-13T00:00:00Z","timestamp":1623542400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,6,13]],"date-time":"2021-06-13T00:00:00Z","timestamp":1623542400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,6,13]],"date-time":"2021-06-13T00:00:00Z","timestamp":1623542400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,6,13]]},"DOI":"10.1109\/newcas50681.2021.9462737","type":"proceedings-article","created":{"date-parts":[[2021,6,28]],"date-time":"2021-06-28T22:09:34Z","timestamp":1624918174000},"page":"1-4","source":"Crossref","is-referenced-by-count":3,"title":["Mixed signal compensation of sampling errors in ADCs due to noisy DPLL clock sources"],"prefix":"10.1109","author":[{"given":"Hao","family":"Zheng","sequence":"first","affiliation":[]},{"given":"Eric","family":"Thompson","sequence":"additional","affiliation":[]},{"given":"John","family":"Hogan","sequence":"additional","affiliation":[]},{"given":"Daniel","family":"O'Hare","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2011.5746236"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2012.6330565"},{"key":"ref6","first-page":"1","article-title":"A 4mW wide bandwidth ring-based fractional-n DPLL with 1.9psrms integrated-jitter","author":"elkholy","year":"2015","journal-title":"2015 IEEE Custom Integrated Circuits Conference (CICC)"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2074950"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1007\/978-90-481-8888-8"},{"key":"ref7","doi-asserted-by":"crossref","DOI":"10.1017\/9781316981238","author":"da dalt","year":"2018","journal-title":"Understanding Jitter and Phase Noise A Circuits and Systems Perspective"},{"key":"ref2","article-title":"ADC Performance Survey 1997-2020","author":"murmann","year":"2013"},{"key":"ref9","first-page":"264c","article-title":"An 8.5mW 5GS\/s 6b flash ADC with dynamic offset calibration in 32nm CMOS SOI","author":"chen","year":"2013","journal-title":"2013 Symposium on VLSI Circuits VLSIC"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS45731.2020.9180391"}],"event":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","location":"Toulon, France","start":{"date-parts":[[2021,6,13]]},"end":{"date-parts":[[2021,6,16]]}},"container-title":["2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9462728\/9462729\/09462737.pdf?arnumber=9462737","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T15:42:57Z","timestamp":1652197377000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9462737\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,6,13]]},"references-count":9,"URL":"https:\/\/doi.org\/10.1109\/newcas50681.2021.9462737","relation":{},"subject":[],"published":{"date-parts":[[2021,6,13]]}}}