{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T10:53:00Z","timestamp":1730285580416,"version":"3.28.0"},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,11]]},"DOI":"10.1109\/ngcas.2018.8572265","type":"proceedings-article","created":{"date-parts":[[2018,12,13]],"date-time":"2018-12-13T20:04:39Z","timestamp":1544731479000},"page":"70-73","source":"Crossref","is-referenced-by-count":0,"title":["Power Optimization of a 0.5V 0.286-to-18MHz ADPLL in 65nm CMOS Process"],"prefix":"10.1109","author":[{"given":"Fredrick Angelo R.","family":"Galapon","sequence":"first","affiliation":[]},{"given":"Mark Allen D.C.","family":"Agaton","sequence":"additional","affiliation":[]},{"given":"Arcel G.","family":"Leynes","sequence":"additional","affiliation":[]},{"given":"Lemuel Neil M.","family":"Noveno","sequence":"additional","affiliation":[]},{"given":"Anastacia B.","family":"Alvarez","sequence":"additional","affiliation":[]},{"given":"Chris Vincent J.","family":"Densing","sequence":"additional","affiliation":[]},{"given":"John Richard E.","family":"Hizon","sequence":"additional","affiliation":[]},{"given":"Marc D.","family":"Rosales","sequence":"additional","affiliation":[]},{"given":"Maria Theresa G.","family":"de Leon","sequence":"additional","affiliation":[]},{"given":"Rico Jossel M.","family":"Maestro","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2010.2087991"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2007.903782"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/S3S.2015.7333528"},{"key":"ref6","doi-asserted-by":"crossref","first-page":"849","DOI":"10.1109\/TCSI.2010.2089559","article-title":"A 0.5-V 0.4&#x2013;2.24-GHz Inductorless Phase-Locked Loop in a System-on-Chip","volume":"58","author":"kuo-hsing","year":"2011","journal-title":"IEEE Transactions on Circuits and Systems I Regular Papers"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2005.846307"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2407370"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2017.8050743"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1587\/elex.13.20160749"},{"key":"ref9","article-title":"A Fast-Lock-In AD-PLL with High-Resolution and Low-Power DCO for SoC Applications","author":"sheng","year":"2006","journal-title":"2010 IEEE Asia Pacific Conference on Circuits and Systems APCCAS"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2014.6865340"}],"event":{"name":"2018 New Generation of CAS (NGCAS)","start":{"date-parts":[[2018,11,20]]},"location":"Valletta, Malta","end":{"date-parts":[[2018,11,23]]}},"container-title":["2018 New Generation of CAS (NGCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8554190\/8572037\/08572265.pdf?arnumber=8572265","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,12,17]],"date-time":"2018-12-17T14:36:22Z","timestamp":1545057382000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8572265\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,11]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/ngcas.2018.8572265","relation":{},"subject":[],"published":{"date-parts":[[2018,11]]}}}