{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,21]],"date-time":"2026-05-21T15:00:37Z","timestamp":1779375637315,"version":"3.53.1"},"reference-count":25,"publisher":"IEEE","license":[{"start":{"date-parts":[[2020,10,24]],"date-time":"2020-10-24T00:00:00Z","timestamp":1603497600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,10,24]],"date-time":"2020-10-24T00:00:00Z","timestamp":1603497600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,10,24]],"date-time":"2020-10-24T00:00:00Z","timestamp":1603497600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,10,24]]},"DOI":"10.1109\/niles50944.2020.9257978","type":"proceedings-article","created":{"date-parts":[[2020,11,18]],"date-time":"2020-11-18T16:50:23Z","timestamp":1605718223000},"page":"1-6","source":"Crossref","is-referenced-by-count":1,"title":["Optimum Sizing of the Sleep Transistor in MTCMOS Technology"],"prefix":"10.1109","author":[{"given":"Sherif M.","family":"Sharroush","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/4.848210"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/1120725.1121056"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2005.48"},{"key":"ref13","article-title":"Subthreshold leakage control techniques for low power digital circuits","author":"kao","year":"1995","journal-title":"Doctor of Philosophy Thesis Massachusetts Institute of Technology USA"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/277044.277180"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2109069"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/1118299.1118435"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.888282"},{"key":"ref18","author":"weste","year":"2011","journal-title":"CMOS VLSI Design A Circuits and Systems Perspective"},{"key":"ref19","author":"ayers","year":"2005","journal-title":"Analysis and Design of Digital Integrated Circuits"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2000.839707"},{"key":"ref3","first-page":"18","article-title":"A high-performance sub-0.25 \/spl mu\/m CMOS technology with multiple thresholds and copper interconnects","author":"su","year":"1998","journal-title":"IEEE Symposium on VLSI Technology Digest of Technical Papers"},{"key":"ref6","first-page":"891","article-title":"Low energy MTCMOS with sleep transistor charge recycling","author":"liu","year":"2007","journal-title":"50th Midwest Symposium on Circuits and Systems"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/4.400426"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1997.597182"},{"key":"ref7","first-page":"973","article-title":"Optimal MTCMOS reactivation under power supply noise and performance constraints","author":"calimera","year":"2008","journal-title":"Design Automation and Test in Europe IEEE"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/9780470545058"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.1999.759726"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1002\/0470033371"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1016\/j.asej.2016.05.005"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ICEDSA.2016.7818522"},{"key":"ref21","first-page":"119","article-title":"Process variation-aware analytical modeling of subthreshold leakage power","author":"anala","year":"2019","journal-title":"International Symposium on Power and Timing Modeling Optimization and Simulation (PATMOS)"},{"key":"ref24","author":"razavi","year":"2017","journal-title":"Design of Analog CMOS Integrated Circuits"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1968.1049902"},{"key":"ref25","year":"0"}],"event":{"name":"2020 2nd Novel Intelligent and Leading Emerging Sciences Conference (NILES)","location":"Giza, Egypt","start":{"date-parts":[[2020,10,24]]},"end":{"date-parts":[[2020,10,26]]}},"container-title":["2020 2nd Novel Intelligent and Leading Emerging Sciences Conference (NILES)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9257809\/9257872\/09257978.pdf?arnumber=9257978","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,6,28]],"date-time":"2022-06-28T17:54:58Z","timestamp":1656438898000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9257978\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,10,24]]},"references-count":25,"URL":"https:\/\/doi.org\/10.1109\/niles50944.2020.9257978","relation":{},"subject":[],"published":{"date-parts":[[2020,10,24]]}}}