{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T21:55:41Z","timestamp":1729634141035,"version":"3.28.0"},"reference-count":46,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,9]]},"DOI":"10.1109\/nocs.2014.7008764","type":"proceedings-article","created":{"date-parts":[[2015,1,19]],"date-time":"2015-01-19T21:46:01Z","timestamp":1421703961000},"page":"72-79","source":"Crossref","is-referenced-by-count":1,"title":["Augmenting manycore programmable accelerators with photonic interconnect technology for the high-end embedded computing domain"],"prefix":"10.1109","author":[{"given":"Marco","family":"Balboni","sequence":"first","affiliation":[]},{"given":"Marta Ortin","family":"Obon","sequence":"additional","affiliation":[]},{"given":"Alessandro","family":"Capotondi","sequence":"additional","affiliation":[]},{"given":"Herve Fankem","family":"Tatenguem","sequence":"additional","affiliation":[]},{"given":"Alberto","family":"Ghiribaldi","sequence":"additional","affiliation":[]},{"given":"Luca","family":"Ramini","sequence":"additional","affiliation":[]},{"given":"Victor","family":"Vinal","sequence":"additional","affiliation":[]},{"given":"Andrea","family":"Marongiu","sequence":"additional","affiliation":[]},{"given":"Davide","family":"Bertozzi","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669152"},{"journal-title":"The HyperCore Processor","year":"2010","author":"plurality ltd","key":"35"},{"key":"17","doi-asserted-by":"crossref","first-page":"441","DOI":"10.1145\/1555815.1555809","article-title":"Phastlane: A rapid transit optical routing network. SIGARCH Comput","volume":"37","author":"cianchetti","year":"2009","journal-title":"Archit News"},{"journal-title":"Multicore DSP+ARM KeyStone II System-on-Chip (SoC)","year":"0","author":"texas instruments inc","key":"36"},{"key":"18","article-title":"Corona: System implications of emerging nanophotonic technology","author":"vantrease","year":"2008","journal-title":"ISCA '08 Int Symposium on Computer Arch"},{"key":"33","first-page":"2182","author":"poletti","year":"2013","journal-title":"VirtualSoC A Full-System Simulation Environment for Massively Parallel Heterogeneous System-on-Chip IEEE International Symposium on Parallel and Distributed Processing"},{"key":"15","article-title":"Re-architecting DRAM memory systems with monolithically integrated silicon photonics","author":"beamer","year":"0","journal-title":"ISCA '10"},{"journal-title":"MPPA 256-Programmable Manycore Processor","year":"0","key":"34"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2007.35"},{"key":"39","doi-asserted-by":"publisher","DOI":"10.1109\/SURV.2011.122111.00069"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1145\/2370816.2370878"},{"year":"0","key":"14"},{"journal-title":"Adapteva","year":"0","key":"37"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/SOPO.2011.5780550"},{"journal-title":"Xilinx Inc Zynq-7000 All Programmable SoC Overview","year":"0","key":"38"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2011.5763134"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2012.6176639"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228568"},{"key":"43","article-title":"Improved utilization of noc channel bandwidth by switch replication for cost-effective multiprocessor systems-on-chip","author":"gilabert villamn","year":"2010","journal-title":"NoCS"},{"key":"42","article-title":"Optimizing the overhead for network-on-chip routing reconfiguration in massively parallel multi-core platforms","author":"balboni","year":"2013","journal-title":"International Symposium on SoC"},{"key":"41","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2010.12"},{"key":"40","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2010.13"},{"year":"0","key":"45"},{"key":"44","article-title":"A complete electronic network interface architecture for global contention-free communication over emerging optical networks-on-chip","author":"ortin","year":"2014","journal-title":"GLSVLSI"},{"key":"47","doi-asserted-by":"publisher","DOI":"10.1111\/j.1467-8659.2007.01012.x"},{"key":"46","doi-asserted-by":"publisher","DOI":"10.1145\/2489068.2489069"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPSW.2013.177"},{"key":"23","article-title":"A library of dual-clock fifos for cost-effective and flexible mpsoc design","author":"strano","year":"0","journal-title":"SAMOS X"},{"key":"24","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2011.6123624"},{"key":"25","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798266"},{"key":"26","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2012.6176441"},{"key":"27","doi-asserted-by":"publisher","DOI":"10.1109\/CLEOPR.2013.6600000"},{"key":"28","doi-asserted-by":"publisher","DOI":"10.1145\/1854273.1854332"},{"key":"29","doi-asserted-by":"publisher","DOI":"10.1109\/HOTI.2008.11"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/5.867687"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1145\/2086696.2086727"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2010.25"},{"key":"1","article-title":"Leveraging optical technology in future bus-based chip multiprocessors","author":"kirman","year":"2006","journal-title":"Micro"},{"key":"30","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555808"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1145\/2401716.2401723"},{"key":"32","first-page":"736","article-title":"Flexible hardware\/software support for message passing on a distributed shared memory architecture","author":"poletti","year":"2005","journal-title":"DATE"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2012.2193932"},{"key":"31","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2005.1"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/TPAMI.2008.275"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1155\/2007\/95859"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2014.321"}],"event":{"name":"2014 Eighth IEEE\/ACM International Symposium on Networks-on-Chip (NoCS)","start":{"date-parts":[[2014,9,17]]},"location":"Ferrara, Italy","end":{"date-parts":[[2014,9,19]]}},"container-title":["2014 Eighth IEEE\/ACM International Symposium on Networks-on-Chip (NoCS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7000615\/7008746\/07008764.pdf?arnumber=7008764","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,22]],"date-time":"2017-06-22T23:54:56Z","timestamp":1498175696000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7008764\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,9]]},"references-count":46,"URL":"https:\/\/doi.org\/10.1109\/nocs.2014.7008764","relation":{},"subject":[],"published":{"date-parts":[[2014,9]]}}}