{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,14]],"date-time":"2025-10-14T20:07:12Z","timestamp":1760472432044,"version":"3.28.0"},"reference-count":30,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,9]]},"DOI":"10.1109\/nocs.2016.7579343","type":"proceedings-article","created":{"date-parts":[[2016,10,3]],"date-time":"2016-10-03T17:38:55Z","timestamp":1475516335000},"page":"1-8","source":"Crossref","is-referenced-by-count":13,"title":["Inter\/intra-chip optical interconnection network: opportunities, challenges, and implementations"],"prefix":"10.1109","author":[{"given":"Peng","family":"Yang","sequence":"first","affiliation":[]},{"given":"Shigeru","family":"Nakamura","sequence":"additional","affiliation":[]},{"given":"Kenichiro","family":"Yashiki","sequence":"additional","affiliation":[]},{"given":"Zhehui","family":"Wang","sequence":"additional","affiliation":[]},{"given":"Luan H. K.","family":"Duong","sequence":"additional","affiliation":[]},{"given":"Zhifei","family":"Wang","sequence":"additional","affiliation":[]},{"given":"Xuanqi","family":"Chen","sequence":"additional","affiliation":[]},{"given":"Yuichi","family":"Nakamura","sequence":"additional","affiliation":[]},{"given":"Jiang","family":"Xu","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2011.38"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815977"},{"key":"ref11","first-page":"1","article-title":"Union: A unified inter\/intrachip optical network for chip multiprocessors","author":"wu","year":"2013","journal-title":"Very Large Scale Integration (VLSI) Systems IEEE Transactions on"},{"key":"ref12","first-page":"1","article-title":"An Inter\/Intra-Chip Optical Network for Manycore Processors","author":"wu","year":"2014","journal-title":"Very Large Scale Integration (VLSI) Systems IEEE Transactions on"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2511039"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2370892"},{"key":"ref15","first-page":"1","article-title":"System-Level Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip","author":"ye","year":"2012","journal-title":"Very Large Scale Integration (VLSI) Systems IEEE Transactions on"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2014.2351584"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1364\/OFC.2015.Th1G.1"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ECOC.2015.7341763"},{"key":"ref19","first-page":"339","article-title":"Helios: a hybrid electrical\/optical switch architecture for modular data centers","volume":"41","author":"farrington","year":"2011","journal-title":"ACM SIGCOMM Computer Communication Review"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2288676"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2511065"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837441"},{"key":"ref3","article-title":"Improve chip pin performance using optical interconnects","author":"wang","year":"2015","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555809"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/GROUP4.2006.1708205"},{"key":"ref5","first-page":"153","article-title":"Corona: System Implications of Emerging Nanophotonic Technology","author":"vantrease","year":"2008","journal-title":"Computer Architecture 35th International Symposium on"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2010.5416626"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2008.78"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1364\/OFC.2015.M2B.6"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2012.13"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1364\/OFC.2016.Th1F.7"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1364\/PS.2014.PM2C.4"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/2600072"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/LPT.2013.2270462"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/50.762889"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2009.5071460"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1364\/OE.15.010553"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2015.0823"}],"event":{"name":"2016 Tenth IEEE\/ACM International Symposium on Networks-on-Chip (NOCS)","start":{"date-parts":[[2016,8,31]]},"location":"Nara, Japan","end":{"date-parts":[[2016,9,2]]}},"container-title":["2016 Tenth IEEE\/ACM International Symposium on Networks-on-Chip (NOCS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7579033\/7579313\/07579343.pdf?arnumber=7579343","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2016,10,11]],"date-time":"2016-10-11T22:42:51Z","timestamp":1476225771000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7579343\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,9]]},"references-count":30,"URL":"https:\/\/doi.org\/10.1109\/nocs.2016.7579343","relation":{},"subject":[],"published":{"date-parts":[[2016,9]]}}}