{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,31]],"date-time":"2025-12-31T12:18:59Z","timestamp":1767183539835,"version":"3.28.0"},"reference-count":28,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,10]]},"DOI":"10.1109\/nocs.2018.8512154","type":"proceedings-article","created":{"date-parts":[[2018,10,30]],"date-time":"2018-10-30T10:00:44Z","timestamp":1540893644000},"page":"1-8","source":"Crossref","is-referenced-by-count":19,"title":["Exploration of Memory and Cluster Modes in Directory-Based Many-Core CMPs"],"prefix":"10.1109","author":[{"given":"Subodha","family":"Charles","sequence":"first","affiliation":[]},{"given":"Chetan Arvind","family":"Patil","sequence":"additional","affiliation":[]},{"given":"Umit Y.","family":"Ogras","sequence":"additional","affiliation":[]},{"given":"Prabhat","family":"Mishra","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","article-title":"Exploring the placement of memory controllers on manycore processors: A case study for Intel SCC","author":"eitschberger","year":"2013","journal-title":"MCC"},{"key":"ref11","doi-asserted-by":"crossref","first-page":"319","DOI":"10.1145\/1854273.1854314","article-title":"Handling the problems and opportunities posed by multiple on-chip memory controllers","author":"awasthi","year":"2010","journal-title":"Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques (PACT)"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2612647"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.43"},{"key":"ref14","first-page":"11","article-title":"Dealing with traffic-area trade-off in direct coherence protocols for many-core CMPs","author":"ros","year":"2009","journal-title":"APPT"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2013.334"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000076"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669166"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/3060517"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2012.6378672"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ICPP.2015.83"},{"key":"ref4","doi-asserted-by":"crossref","DOI":"10.1007\/978-94-007-3958-1","author":"ogras","year":"2013","journal-title":"Modeling Analysis and Optimization of Network-on-Chip Communication Architectures"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/WWC.2001.990739"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.4378780"},{"key":"ref6","first-page":"1","article-title":"The gem5 simulator","volume":"39","author":"binkert","year":"2011","journal-title":"CA News"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555810"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2039370.2039405"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.31"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.4378783"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2010.5434077"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2016.25"},{"journal-title":"Intel Core i7 –900 Processor","year":"0","key":"ref20"},{"key":"ref22","first-page":"1","article-title":"Atlas: A scalable and high-performance scheduling algorithm for multiple memory controllers","author":"kim","year":"2010","journal-title":"HPCA"},{"journal-title":"Intel Xeon Phi Processor 7210","year":"0","key":"ref21"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2011229"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2009.4919636"},{"key":"ref26","doi-asserted-by":"crossref","DOI":"10.1145\/225830.223990","article-title":"The splash-2 programs: Characterization and methodological considerations","author":"woo","year":"1995","journal-title":"Computer Architecture"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669172"}],"event":{"name":"2018 Twelfth IEEE\/ACM International Symposium on Networks-on-Chip (NOCS)","start":{"date-parts":[[2018,10,4]]},"location":"Turin","end":{"date-parts":[[2018,10,5]]}},"container-title":["2018 Twelfth IEEE\/ACM International Symposium on Networks-on-Chip (NOCS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8501313\/8512146\/08512154.pdf?arnumber=8512154","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,26]],"date-time":"2022-01-26T18:16:25Z","timestamp":1643220985000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8512154\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,10]]},"references-count":28,"URL":"https:\/\/doi.org\/10.1109\/nocs.2018.8512154","relation":{},"subject":[],"published":{"date-parts":[[2018,10]]}}}