{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T10:55:28Z","timestamp":1730285728796,"version":"3.28.0"},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,11]]},"DOI":"10.1109\/norchip.2013.6702001","type":"proceedings-article","created":{"date-parts":[[2014,1,10]],"date-time":"2014-01-10T20:09:12Z","timestamp":1389384552000},"page":"1-4","source":"Crossref","is-referenced-by-count":2,"title":["3D volumetric display design challenges"],"prefix":"10.1109","author":[{"given":"Kriss","family":"Osmanis","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gatis","family":"Valters","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ilmars","family":"Osmanis","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"Xilinx Memory Interface Solutions User Guide","year":"2010","key":"13"},{"year":"2008","key":"14"},{"journal-title":"Virtex-6 FPGA GTX Transceivers User Guide","year":"2011","key":"11"},{"journal-title":"Video Electronics Standards Association 860 Hillview Court","year":"0","key":"12"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/MSPEC.2005.1413728"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1002\/0471443395.img093"},{"journal-title":"Virtex-5 FPGA Data Sheet DC and Switching Characteristics","year":"2013","key":"10"},{"key":"1","first-page":"92","article-title":"Adding depth to displays","volume":"41","year":"2005","journal-title":"Laser Focus World"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2005.276"},{"key":"6","first-page":"1531","volume":"34","author":"sullivan","year":"2003","journal-title":"A Solid-state Multi-planar Volumetric Display"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/IC3D.2012.6615132"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/BEC.2012.6376815"},{"journal-title":"DisplayPort Developer Conference","year":"2010","author":"display","key":"9"},{"journal-title":"100 Power Tips for FPGA Designers","year":"2011","author":"stavinov","key":"8"}],"event":{"name":"2013 NORCHIP","start":{"date-parts":[[2013,11,11]]},"location":"Vilnius, Lithuania","end":{"date-parts":[[2013,11,12]]}},"container-title":["2013 NORCHIP"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6693155\/6701993\/06702001.pdf?arnumber=6702001","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,22]],"date-time":"2017-03-22T21:39:59Z","timestamp":1490218799000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6702001\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,11]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/norchip.2013.6702001","relation":{},"subject":[],"published":{"date-parts":[[2013,11]]}}}