{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T00:56:05Z","timestamp":1729644965004,"version":"3.28.0"},"reference-count":23,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,10]]},"DOI":"10.1109\/norchip.2015.7364376","type":"proceedings-article","created":{"date-parts":[[2015,12,28]],"date-time":"2015-12-28T16:35:01Z","timestamp":1451320501000},"page":"1-8","source":"Crossref","is-referenced-by-count":2,"title":["Design of a hybrid multicore platform for high performance reconfigurable computing"],"prefix":"10.1109","author":[{"given":"Waqar","family":"Hussain","sequence":"first","affiliation":[]},{"given":"Henry","family":"Hoffmann","sequence":"additional","affiliation":[]},{"given":"Tapani","family":"Ahonen","sequence":"additional","affiliation":[]},{"given":"Jari","family":"Nurmi","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISSOC.2010.5625562"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4020-5530-0_5"},{"key":"ref12","first-page":"610","article-title":"Definition and SIMD implementation of a multi-processing architecture approach on FPGA","author":"bonnot","year":"0","journal-title":"Proceedings of the Design Automation and Test in Europe (DATE)"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228568"},{"article-title":"Designing Network-Based Single-Chip System Architectures","year":"2006","author":"ahonen","key":"ref14"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2009.5272353"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1007\/s11265-011-0642-6"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISSoC.2012.6376372"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2013.6567599"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/12.859540"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2222814"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.1960.1157266"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.912075"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/HPEC.2014.7040951"},{"key":"ref8","first-page":"39","article-title":"Flexeos Embedded FPGA Solution","volume":"40","author":"voros","year":"0","journal-title":"Dynamic System Reconfiguration in Heterogeneous Platforms Lecture Notes in Electrical Engineering"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2442116.2442120"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228567"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/1736020.1736044"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2007.364559"},{"key":"ref20","doi-asserted-by":"crossref","first-page":"61","DOI":"10.1007\/978-3-540-45234-8_7","article-title":"ADRES: An architecture with tightly coupled VLIW processor and coarse-grained reconfigurable matrix","volume":"2778","author":"mei","year":"2003","journal-title":"Field-Programmable Logic and Applications"},{"key":"ref22","first-page":"2","article-title":"Altera Product Catalog. 2015","year":"2014","journal-title":"Data Release"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1023\/A:1024499601571"},{"key":"ref23","doi-asserted-by":"crossref","first-page":"203","DOI":"10.1109\/TCAD.2006.884574","article-title":"Measuring the Gap Between FPGAs and ASICs","volume":"26","author":"ian","year":"2007","journal-title":"Computer-Aided Design of Integrated Circuits and Systems IEEE Transactions on"}],"event":{"name":"2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)","start":{"date-parts":[[2015,10,26]]},"location":"Oslo, Norway","end":{"date-parts":[[2015,10,28]]}},"container-title":["2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP &amp; International Symposium on System-on-Chip (SoC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7360269\/7364350\/07364376.pdf?arnumber=7364376","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,23]],"date-time":"2017-06-23T22:36:50Z","timestamp":1498257410000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7364376\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,10]]},"references-count":23,"URL":"https:\/\/doi.org\/10.1109\/norchip.2015.7364376","relation":{},"subject":[],"published":{"date-parts":[[2015,10]]}}}