{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T16:58:28Z","timestamp":1729616308778,"version":"3.28.0"},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,11]]},"DOI":"10.1109\/norchip.2016.7792915","type":"proceedings-article","created":{"date-parts":[[2016,12,24]],"date-time":"2016-12-24T08:53:48Z","timestamp":1482569628000},"page":"1-4","source":"Crossref","is-referenced-by-count":1,"title":["A novel random approach to diagnostic test generation"],"prefix":"10.1109","author":[{"given":"Emmanuel Ovie","family":"Osimiry","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Raimund","family":"Ubar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sergei","family":"Kostin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jaan","family":"Raik","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/BEC.2016.7743733"},{"key":"ref11","first-page":"785","article-title":"A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortran","author":"fujiwara","year":"1985","journal-title":"Int Test Conference"},{"key":"ref12","first-page":"1929","article-title":"Combinational Profiles of Sequential Benchmark Circuits","author":"bryan","year":"1989","journal-title":"Int Symp on Circuits and Systems"},{"key":"ref13","doi-asserted-by":"crossref","first-page":"44","DOI":"10.1109\/54.867894","article-title":"RT-level ITC'99 Benchmarks and First ATPG Results","volume":"17","author":"reorda","year":"2000","journal-title":"Proc of the IEEE Design & Test of Computers"},{"journal-title":"Digital Systems Testing and Testable Design","year":"1994","author":"breuer","key":"ref14"},{"journal-title":"VLSI Test Principles and Architectures Design for Testability","year":"2006","key":"ref4"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2014.6847826"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2010.5699237"},{"journal-title":"Digital System Test and Testable Design Using HDL Models and Architectures","year":"2010","key":"ref5"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.1998.741661"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1017\/CBO9780511816321"},{"key":"ref2","article-title":"Cramming More Components onto Integrated Circuits","volume":"38","author":"moore","year":"1965","journal-title":"reprinted from Proc IEEE"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/35.769283"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2007.15"}],"event":{"name":"2016 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","start":{"date-parts":[[2016,11,1]]},"location":"Copenhagen, Denmark","end":{"date-parts":[[2016,11,2]]}},"container-title":["2016 IEEE Nordic Circuits and Systems Conference (NORCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7784514\/7792873\/07792915.pdf?arnumber=7792915","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,25]],"date-time":"2017-06-25T02:40:56Z","timestamp":1498358456000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7792915\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,11]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/norchip.2016.7792915","relation":{},"subject":[],"published":{"date-parts":[[2016,11]]}}}