{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T06:03:43Z","timestamp":1725429823165},"reference-count":31,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,10]]},"DOI":"10.1109\/norchip.2017.8124946","type":"proceedings-article","created":{"date-parts":[[2017,11,30]],"date-time":"2017-11-30T22:01:19Z","timestamp":1512079279000},"page":"1-6","source":"Crossref","is-referenced-by-count":0,"title":["Exploration of FPGA architectures for tight coupled accelerators in a 22nm FDSOI technology"],"prefix":"10.1109","author":[{"given":"Heiner","family":"Bauer","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sebastian","family":"Hoppner","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Johannes","family":"Partzsch","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dennis","family":"Walter","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Christian","family":"Mayr","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Florian","family":"Schraut","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Holger","family":"Eisenreich","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref31","first-page":"1","article-title":"Design technology co-optimization of strain-induced layout effects in 14nm UTBB-FDSOI CMOS: Enablement and assessment of continuous-RX designs","author":"berthelon","year":"2016","journal-title":"IEEE Symp VLSI Technol"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2016.7577325"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2006.311270"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.859319"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/1046192.1046195"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.1990.124841"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.824300"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/329166.329171"},{"journal-title":"Quantifying and Exploring the Gap between FPGAs and ASICs","year":"2009","author":"kuon","key":"ref16"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2011.6132684"},{"key":"ref18","article-title":"Dynamic instruction set extension of microprocessors with embedded FPGAs","author":"bauer","year":"2017","journal-title":"Diploma thesis Technische Universitat Dresden"},{"journal-title":"Modellierung und Analyse arithmetikorientierter eFPGA-Architekturen","year":"2010","author":"neumann","key":"ref19"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2013.6718327"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.821545"},{"journal-title":"Architecture and algorithms for field programmable gate arrays with embedded memory","year":"1997","author":"wilton","key":"ref27"},{"journal-title":"Augmenting a microprocessor with reconfigurable hardware","year":"2000","author":"hauser","key":"ref3"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/RECONF.2006.307777"},{"journal-title":"Logical Effort Designing Fast CMOS Circuits","year":"1999","author":"sutherland","key":"ref29"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1996.564773"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1278480.1278678"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2007.370385"},{"journal-title":"Stratix 10 GX\/SX Device Overview Intel Programmable Solutions Group","year":"2016","key":"ref2"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1007\/s11265-008-0211-9"},{"journal-title":"Zynq UltraScale+ MPSoC Data Sheet Overview","year":"2017","key":"ref1"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/2617593"},{"key":"ref22","article-title":"GCC-plugin for automated accelerator generation and integration on hybrid FPGA-SoCs","author":"vogt","year":"2015","journal-title":"Proc of the Int Workshop on FPGAs for Software Programmers"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2016.7838029"},{"journal-title":"Berkeley Logic Synthesis and Verification Group","article-title":"ABC: A system for sequential synthesis and verification","year":"2016","key":"ref24"},{"key":"ref23","article-title":"Logic synthesis and optimization benchmarks user guide, version 3.0","author":"yang","year":"1991","journal-title":"Microelectronics Centre North Carolina"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/1950413.1950447"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-5145-4"}],"event":{"name":"2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","start":{"date-parts":[[2017,10,23]]},"location":"Linkoping","end":{"date-parts":[[2017,10,25]]}},"container-title":["2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8119342\/8124941\/08124946.pdf?arnumber=8124946","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,1,15]],"date-time":"2018-01-15T22:52:59Z","timestamp":1516056779000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8124946\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,10]]},"references-count":31,"URL":"https:\/\/doi.org\/10.1109\/norchip.2017.8124946","relation":{},"subject":[],"published":{"date-parts":[[2017,10]]}}}