{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T00:02:36Z","timestamp":1729641756200,"version":"3.28.0"},"reference-count":19,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,10]]},"DOI":"10.1109\/norchip.2017.8124976","type":"proceedings-article","created":{"date-parts":[[2017,11,30]],"date-time":"2017-11-30T22:01:19Z","timestamp":1512079279000},"page":"1-6","source":"Crossref","is-referenced-by-count":0,"title":["Variable-accuracy bit-serial multiplication with row bypassing for ultra low power"],"prefix":"10.1109","author":[{"given":"Yue","family":"Lu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tom J.","family":"Kazmierski","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCOM.1976.1093315"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1983.1676341"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ARITH.1985.6158941"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/12.338107"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/13.485228"},{"key":"ref15","doi-asserted-by":"crossref","first-page":"185","DOI":"10.1049\/ip-e.1993.0026","article-title":"Radix-2n multiplier structures: A structured design methodology","volume":"140","author":"ibrahim","year":"1993","journal-title":"IEE Proceedings E (Computers and Digital Techniques)"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1973.223648"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1049\/el:20050464"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/SOCCON.2009.5398054"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/12.863039"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1147\/rd.504.0469"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2009.2034764"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2011.51"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2011.6105401"},{"key":"ref8","first-page":"13","article-title":"Multiplier energy reduction through bypassing of partial products","volume":"2","author":"ohban","year":"2002","journal-title":"Circuits and Systems 2002 APCCAS'02 2002 Asia-Pacific Conference on"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2006.320900"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1016\/j.future.2013.01.010"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.21533\/scjournal.v3i2.8"},{"key":"ref9","first-page":"114","article-title":"High performance bit-serial multiplication","volume":"86","author":"scanlon","year":"1986","journal-title":"Proc IEEE ICCD&#x2019;"}],"event":{"name":"2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","start":{"date-parts":[[2017,10,23]]},"location":"Linkoping","end":{"date-parts":[[2017,10,25]]}},"container-title":["2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8119342\/8124941\/08124976.pdf?arnumber=8124976","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,10,7]],"date-time":"2019-10-07T05:32:42Z","timestamp":1570426362000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8124976\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,10]]},"references-count":19,"URL":"https:\/\/doi.org\/10.1109\/norchip.2017.8124976","relation":{},"subject":[],"published":{"date-parts":[[2017,10]]}}}