{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T10:56:08Z","timestamp":1730285768365,"version":"3.28.0"},"reference-count":26,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,10]]},"DOI":"10.1109\/norchip.2017.8124987","type":"proceedings-article","created":{"date-parts":[[2017,11,30]],"date-time":"2017-11-30T17:01:19Z","timestamp":1512061279000},"page":"1-6","source":"Crossref","is-referenced-by-count":2,"title":["Power mitigation of a heterogeneous multicore architecture by frequency scaling in an OFDM receiver test case"],"prefix":"10.1109","author":[{"given":"Sajjad","family":"Nouri","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jari","family":"Nurmi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1007\/s11265-016-1142-5"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISSOC.2014.6972451"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228568"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2591513.2591553"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2442116.2442120"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2007.4380681"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-31128-4_44"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488874"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/SAMOS.2013.6621112"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2014.6974729"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1736020.1736044"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2002.997877"},{"key":"ref6","first-page":"1410","article-title":"Dynamic Thermal Management in 3D Multicore Architectures","author":"coskun","year":"2005","journal-title":"Design Automation and Test in Europe Conference and Exhibition"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228567"},{"key":"ref8","first-page":"259","article-title":"DAC Design Automation Conference","author":"hoffmann","year":"2012","journal-title":"Self-aware Computing in the Angstrom Processor"},{"key":"ref7","first-page":"123","article-title":"System level anaysis of fast, per-core DVFS using on-chip switching regulators","author":"kim","year":"2008","journal-title":"Proc Int Symp High Performance Computer Architecture (HPCA)"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2016.2573586"},{"key":"ref9","article-title":"HARP2: An X-Scale Reconfigurable Accelerator-Rich Platform for Massively-Parallel Signal Processing Algorithms","author":"hussain","year":"2015","journal-title":"J Sign Process Syst Springer"},{"key":"ref1","article-title":"Cramming more components onto integrated circuits","volume":"38","author":"moore","year":"1965","journal-title":"Electronics"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2014.6858424"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2011.160"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/2968456.2974043"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2009.5272353"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4020-5530-0_5"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2017.2706691"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2008.4629990"}],"event":{"name":"2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","start":{"date-parts":[[2017,10,23]]},"location":"Linkoping","end":{"date-parts":[[2017,10,25]]}},"container-title":["2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8119342\/8124941\/08124987.pdf?arnumber=8124987","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,1,15]],"date-time":"2018-01-15T17:52:57Z","timestamp":1516038777000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8124987\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,10]]},"references-count":26,"URL":"https:\/\/doi.org\/10.1109\/norchip.2017.8124987","relation":{},"subject":[],"published":{"date-parts":[[2017,10]]}}}