{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T10:56:13Z","timestamp":1730285773376,"version":"3.28.0"},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,10]]},"DOI":"10.1109\/norchip.2018.8573457","type":"proceedings-article","created":{"date-parts":[[2018,12,14]],"date-time":"2018-12-14T01:07:05Z","timestamp":1544749625000},"page":"1-10","source":"Crossref","is-referenced-by-count":1,"title":["Design and Implementation of Multi-Purpose DCT\/DST-Specific Accelerator on Heterogeneous Multicore Architecture"],"prefix":"10.1109","author":[{"given":"Sajjad","family":"Nouri","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ramin","family":"Ghaznavi-Youvalari","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jari","family":"Nurmi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/NORCHIP.2017.8124987"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2017.2706691"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSTSP.2013.2270429"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.2017.7952416"},{"key":"ref11","article-title":"A Fast Computational Algorithm for the Discrete Co- sine Transform","volume":"com 25","author":"chen","year":"1977","journal-title":"IEEE Transactions on Communications"},{"key":"ref5","article-title":"Hierarchically heterogeneous network-onchip","author":"ahonen","year":"2007","journal-title":"Proceedings of the IEEE International Conference on Computer as a Tool (EUROCON’07)"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2017.8050323"},{"key":"ref7","first-page":"1","article-title":"Kvazaar 4K HEVC intra encoder on FPGA accelerated airframe server","author":"sj\u00f6vall","year":"2017","journal-title":"Signal Processing Systems (SiPS) 2017 IEEE Workshop on"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSTSP.2013.2270429"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2008.4629990"},{"key":"ref1","first-page":"7798","article-title":"Recent developments in standardization of High Efficiency Video Coding (HEVC)","author":"sullivan","year":"2010","journal-title":"Proc 33rd SPIE Appl Dig Image Process"}],"event":{"name":"2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","start":{"date-parts":[[2018,10,30]]},"location":"Tallinn","end":{"date-parts":[[2018,10,31]]}},"container-title":["2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8552599\/8573449\/08573457.pdf?arnumber=8573457","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,27]],"date-time":"2022-01-27T04:58:07Z","timestamp":1643259487000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8573457\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,10]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/norchip.2018.8573457","relation":{},"subject":[],"published":{"date-parts":[[2018,10]]}}}