{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T09:24:30Z","timestamp":1763457870782,"version":"3.44.0"},"reference-count":13,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,10,1]],"date-time":"2019-10-01T00:00:00Z","timestamp":1569888000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,10,1]],"date-time":"2019-10-01T00:00:00Z","timestamp":1569888000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,10]]},"DOI":"10.1109\/norchip.2019.8906953","type":"proceedings-article","created":{"date-parts":[[2019,11,25]],"date-time":"2019-11-25T14:03:10Z","timestamp":1574690590000},"page":"1-6","source":"Crossref","is-referenced-by-count":1,"title":["An All-Digital Duty-Cycle Corrector for Parallel High-Speed I\/O Links"],"prefix":"10.1109","author":[{"given":"Nico","family":"Angeli","sequence":"first","affiliation":[{"name":"Integrated Electronic Systems Lab,TU Darmstadt Merckstrasse 25, Darmstadt,Germany,64283"}]},{"given":"Klaus","family":"Hofmann","sequence":"additional","affiliation":[{"name":"Integrated Electronic Systems Lab,TU Darmstadt Merckstrasse 25, Darmstadt,Germany,64283"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7418033"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2015.2418155"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2018.2811412"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.914286"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2260186"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2015.2468911"},{"key":"ref6","article-title":"An all-digital 50% duty-cycle corrector","author":"wang","year":"0","journal-title":"IEEE Int Symp on Circuits and Systems (ISCAS)"},{"key":"ref5","doi-asserted-by":"crossref","first-page":"1524","DOI":"10.1109\/TVLSI.2011.2158011","article-title":"A 0.31&#x2013;1 ghz fast-corrected duty-cycle corrector with successive approximation register for ddr dram applications","volume":"20","author":"min","year":"2012","journal-title":"IEEE Trans VLSI Syst"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2012.6243808"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757506"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2394486"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2185369"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2018.8351118"}],"event":{"name":"2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","start":{"date-parts":[[2019,10,29]]},"location":"Helsinki, Finland","end":{"date-parts":[[2019,10,30]]}},"container-title":["2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8894146\/8906892\/08906953.pdf?arnumber=8906953","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,19]],"date-time":"2025-08-19T18:09:28Z","timestamp":1755626968000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8906953\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,10]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/norchip.2019.8906953","relation":{},"subject":[],"published":{"date-parts":[[2019,10]]}}}