{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,26]],"date-time":"2026-03-26T07:43:38Z","timestamp":1774511018506,"version":"3.50.1"},"reference-count":6,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,8,20]],"date-time":"2025-08-20T00:00:00Z","timestamp":1755648000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,8,20]],"date-time":"2025-08-20T00:00:00Z","timestamp":1755648000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,8,20]]},"DOI":"10.1109\/nvmsa66678.2025.00008","type":"proceedings-article","created":{"date-parts":[[2026,3,25]],"date-time":"2026-03-25T19:54:18Z","timestamp":1774468458000},"page":"1-6","source":"Crossref","is-referenced-by-count":0,"title":["Ultra-Low Power LDPC Decoder Design for NAND Flash Storage"],"prefix":"10.1109","author":[{"given":"Duen-Yih","family":"Teng","sequence":"first","affiliation":[{"name":"Silicon Motion Technology Corp.,Storage Research Dept.,Hsinchu,Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mao-Ruei","family":"Li","sequence":"additional","affiliation":[{"name":"Silicon Motion Technology Corp.,Storage Research Dept.,Hsinchu,Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shiuan-Hao","family":"Kuo","sequence":"additional","affiliation":[{"name":"Silicon Motion Technology Corp.,Storage Research Dept.,Hsinchu,Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TIT.1962.1057683"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1049\/el:19961141"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISITA.2008.4895387"},{"key":"ref4","article-title":"Method for developing acceleration models for electronic component failure mechanisms","volume-title":"Stan-dard JESD91A","year":"2003"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/PIMRC.2010.5671820"},{"key":"ref6","volume-title":"Study of undetected error probability of ieee 802.3 crc-32 code for mttfpa analysis","author":"Prieto","year":"2015"}],"event":{"name":"2025 IEEE 14th Non-Volatile Memory Systems and Applications Symposium (NVMSA)","location":"Singapore, Singapore","start":{"date-parts":[[2025,8,20]]},"end":{"date-parts":[[2025,8,22]]}},"container-title":["2025 IEEE 14th Non-Volatile Memory Systems and Applications Symposium (NVMSA)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11449246\/11449319\/11449331.pdf?arnumber=11449331","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,3,26]],"date-time":"2026-03-26T05:52:07Z","timestamp":1774504327000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11449331\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,8,20]]},"references-count":6,"URL":"https:\/\/doi.org\/10.1109\/nvmsa66678.2025.00008","relation":{},"subject":[],"published":{"date-parts":[[2025,8,20]]}}}