{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,12]],"date-time":"2026-04-12T02:34:16Z","timestamp":1775961256731,"version":"3.50.1"},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,10]]},"DOI":"10.1109\/nvmts.2015.7457484","type":"proceedings-article","created":{"date-parts":[[2016,4,25]],"date-time":"2016-04-25T21:45:12Z","timestamp":1461620712000},"page":"1-6","source":"Crossref","is-referenced-by-count":15,"title":["Neuromorphic hybrid RRAM-CMOS RBM architecture"],"prefix":"10.1109","author":[{"given":"Manan","family":"Suri","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Vivek","family":"Parmar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ashwani","family":"Kumar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Damien","family":"Querlioz","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Fabien","family":"Alibart","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1162\/neco.2006.18.7.1527"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2011.6055294"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2013.2263000"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TIE.2013.2275966"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2014.6865325"},{"key":"ref5","doi-asserted-by":"crossref","first-page":"971","DOI":"10.1109\/IJCNN.2003.1223822","article-title":"A VLSI implementation of mixed-signal mode bipolar neuron circuitry","volume":"2","author":"pan","year":"2003","journal-title":"In Neural Networks 2003 Proceedings of the International Joint Conference on"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-TSA.2012.6210125"},{"key":"ref8","first-page":"926","article-title":"A practical guide to training restricted Boltzmann machines","volume":"9","author":"hinton","year":"2010","journal-title":"Momentum"},{"key":"ref7","doi-asserted-by":"crossref","first-page":"1425","DOI":"10.7873\/DATE.2015.0362","article-title":"Variation-Aware, Reliability-Emphasized Design and Optimization of RRAM Using SPICE Model","author":"h li","year":"2015","journal-title":"Design Automation Test in Europe Conference Exhibition (DATE)"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/IJCNN.2015.7280603"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2011.6131488"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1016\/j.engappai.2014.09.013"}],"event":{"name":"2015 15th Non-Volatile Memory Technology Symposium (NVMTS)","location":"Beijing, China","start":{"date-parts":[[2015,10,12]]},"end":{"date-parts":[[2015,10,14]]}},"container-title":["2015 15th Non-Volatile Memory Technology Symposium (NVMTS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7451913\/7457421\/07457484.pdf?arnumber=7457484","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,9,7]],"date-time":"2019-09-07T01:01:00Z","timestamp":1567818060000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7457484\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,10]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/nvmts.2015.7457484","relation":{},"subject":[],"published":{"date-parts":[[2015,10]]}}}