{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T06:17:22Z","timestamp":1725603442767},"reference-count":5,"publisher":"IEEE","license":[{"start":{"date-parts":[[2018,10,1]],"date-time":"2018-10-01T00:00:00Z","timestamp":1538352000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2018,10,1]],"date-time":"2018-10-01T00:00:00Z","timestamp":1538352000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,10]]},"DOI":"10.1109\/nvmts.2018.8603113","type":"proceedings-article","created":{"date-parts":[[2019,1,24]],"date-time":"2019-01-24T02:16:50Z","timestamp":1548296210000},"page":"1-5","source":"Crossref","is-referenced-by-count":0,"title":["Accurate error bit mode analysis of STT-MRAM chip with a novel current measurement module implemented to gigabit class memory test system"],"prefix":"10.1109","author":[{"given":"R.","family":"Tamura","sequence":"first","affiliation":[{"name":"Advantest Corporation, Meiwa-machi, Gunma, 370-0718, Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"I.","family":"Mori","sequence":"additional","affiliation":[{"name":"Advantest Corporation, Meiwa-machi, Gunma, 370-0718, Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"N.","family":"Watanabe","sequence":"additional","affiliation":[{"name":"Advantest Corporation, Meiwa-machi, Gunma, 370-0718, Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"H.","family":"Koike","sequence":"additional","affiliation":[{"name":"Center for Innovative Integrated Electronic Systems, Tohoku University, Sendai, 980-0845, Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"T.","family":"Endoh","sequence":"additional","affiliation":[{"name":"Center for Innovative Integrated Electronic Systems, Tohoku University, Sendai, 980-0845, Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"ref4","DOI":"10.7567\/JJAP.53.04ED13"},{"key":"ref3","first-page":"1","article-title":"Embedded Nonvolatile Memory with STT-MRAMs and its Application for Nonvolatile Brain-Inspired VLSIs","author":"endoh","year":"2017","journal-title":"2017 International Symposia on VLSI Technology Systems and Applications"},{"key":"ref5","first-page":"75","article-title":"A 600 MHz MTJ-based nonvolatile latch making use of incubation time in MTJ switching","author":"endoh","year":"2011","journal-title":"IEEE International Electron Devices Meeting(IEDM) Technical Digest"},{"doi-asserted-by":"publisher","key":"ref2","DOI":"10.1109\/JETCAS.2016.2547704"},{"doi-asserted-by":"publisher","key":"ref1","DOI":"10.1109\/VLSIC.2012.6243782"}],"event":{"name":"2018 Non-Volatile Memory Technology Symposium (NVMTS)","start":{"date-parts":[[2018,10,22]]},"location":"Sendai, Japan","end":{"date-parts":[[2018,10,24]]}},"container-title":["2018 Non-Volatile Memory Technology Symposium (NVMTS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8589963\/8603098\/08603113.pdf?arnumber=8603113","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,9,15]],"date-time":"2022-09-15T19:39:08Z","timestamp":1663270748000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8603113\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,10]]},"references-count":5,"URL":"https:\/\/doi.org\/10.1109\/nvmts.2018.8603113","relation":{},"subject":[],"published":{"date-parts":[[2018,10]]}}}