{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,19]],"date-time":"2025-09-19T08:01:29Z","timestamp":1758268889243,"version":"3.44.0"},"reference-count":22,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,10,1]],"date-time":"2019-10-01T00:00:00Z","timestamp":1569888000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,10,1]],"date-time":"2019-10-01T00:00:00Z","timestamp":1569888000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,10]]},"DOI":"10.1109\/nvmts47818.2019.8986214","type":"proceedings-article","created":{"date-parts":[[2020,2,10]],"date-time":"2020-02-10T22:36:59Z","timestamp":1581374219000},"page":"1-4","source":"Crossref","is-referenced-by-count":6,"title":["Functionality Enhanced Memories for Edge-AI Embedded Systems"],"prefix":"10.1109","author":[{"given":"Alexandre","family":"Levisse","sequence":"first","affiliation":[{"name":"ESL, Swiss Federal Institute of Technology Lausanne (EPFL),Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Marco","family":"Rios","sequence":"additional","affiliation":[{"name":"ESL, Swiss Federal Institute of Technology Lausanne (EPFL),Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"W.-A.","family":"Simon","sequence":"additional","affiliation":[{"name":"ESL, Swiss Federal Institute of Technology Lausanne (EPFL),Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"P.-E.","family":"Gaillardon","sequence":"additional","affiliation":[{"name":"University of Utah,Laboratory for NanoIntegrated Systems (LNIS),USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"D.","family":"Atienza","sequence":"additional","affiliation":[{"name":"ESL, Swiss Federal Institute of Technology Lausanne (EPFL),Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2010.2070050"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIC.2019.8778129"},{"journal-title":"Reram embedded super low-power consumption mcu mn101l","year":"0","key":"ref12"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2013.6487708"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2016.7838346"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2015.7409671"},{"journal-title":"Functionality-enhanced devices an alternative to moore’s law","year":"2019","author":"gaillardon","key":"ref16"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/GCCE.2017.8229395"},{"key":"ref18","article-title":"14.6 a 0.62 mw ultra-low-power convolutional-neural-network face-recognition processor and a cis integrated with always-on haar-like face detector","author":"bong","year":"2017","journal-title":"IEEE ISSCC"},{"journal-title":"Rc-nvm Dual-addressing non-volatile memory architecture supporting both row and column memory accesses","year":"2019","author":"li","key":"ref19"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2014.7046995"},{"journal-title":"Metal–oxide rram","year":"2012","author":"wong","key":"ref3"},{"journal-title":"ACM GLSVLSI","article-title":"Blade: A bitline accelerator for devices on the edge","year":"2019","key":"ref6"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317741"},{"key":"ref8","article-title":"Resistive switching memory architecture based on polarity controllable selectors","author":"levisse","year":"2018","journal-title":"IEEE TNANO"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-SoC.2019.8920317"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JXCDC.2018.2821638"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2012.6479004"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2016.2590142"},{"journal-title":"Multi-port 1r1w transpose magnetic random access memory by hierarchical bit-line switching","year":"2019","author":"chang","key":"ref20"},{"key":"ref22","article-title":"Rram-vac: A variability-aware controller for rram-based memory architectures","author":"tuli","year":"2020","journal-title":"IEEE\/ACM ASP-DAC"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2019.2908967"}],"event":{"name":"2019 19th Non-Volatile Memory Technology Symposium (NVMTS)","start":{"date-parts":[[2019,10,28]]},"location":"Durham, NC, USA","end":{"date-parts":[[2019,10,30]]}},"container-title":["2019 19th Non-Volatile Memory Technology Symposium (NVMTS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8979203\/8986154\/08986214.pdf?arnumber=8986214","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,9,1]],"date-time":"2025-09-01T19:25:43Z","timestamp":1756754743000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8986214\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,10]]},"references-count":22,"URL":"https:\/\/doi.org\/10.1109\/nvmts47818.2019.8986214","relation":{},"subject":[],"published":{"date-parts":[[2019,10]]}}}