{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T23:50:33Z","timestamp":1740181833307,"version":"3.37.3"},"reference-count":43,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2021,1,1]],"date-time":"2021-01-01T00:00:00Z","timestamp":1609459200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by-nc-nd\/4.0\/"}],"funder":[{"DOI":"10.13039\/501100001700","name":"Doctoral Program for World-Leading Innovative and Smart Education, Ministry of Education, Culture, Sports, Science and Technology","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100001700","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100007053","name":"VLSI Design and Education Center, the University of Tokyo in collaboration with Cadence Design Systems, Inc., Synopsys, Inc., and Mentor Graphics, Inc.","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100007053","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Open J. Circuits Syst."],"published-print":{"date-parts":[[2021]]},"DOI":"10.1109\/ojcas.2020.3035402","type":"journal-article","created":{"date-parts":[[2020,11,9]],"date-time":"2020-11-09T20:49:33Z","timestamp":1604954973000},"page":"144-155","source":"Crossref","is-referenced-by-count":1,"title":["MOSDA: On-Chip Memory Optimized Sparse Deep Neural Network Accelerator With Efficient Index Matching"],"prefix":"10.1109","volume":"2","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-9947-7789","authenticated-orcid":false,"given":"Hongjie","family":"Xu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jun","family":"Shiomi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5198-0668","authenticated-orcid":false,"given":"Hidetoshi","family":"Onodera","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1145\/2898361"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1007\/s11263-015-0816-y"},{"journal-title":"SPARSKIT A Basic Tool Kit for Sparse Matrix Computations","year":"1994","author":"saad","key":"ref33"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/3386263.3406925"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2019.00042"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.90"},{"key":"ref37","first-page":"1097","article-title":"ImageNet classification with deep convolutional neural networks","author":"krizhevsky","year":"2012","journal-title":"Advances in Neural Information Processing Systems 25"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/4.509850"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2946771"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/3140659.3080254"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310262"},{"journal-title":"To prune or not to prune exploring the efficacy of pruning for model compression","year":"2018","author":"zhu","key":"ref40"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080246"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2636225"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2019.2910232"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001138"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750389"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIC.2017.8008534"},{"journal-title":"MEC Memory-efficient convolution for deep neural network","year":"2017","author":"cho","key":"ref17"},{"key":"ref18","first-page":"150c","article-title":"A 7.3 M output non-zeros\/J sparse matrix-matrix multiplication accelerator using memory reconfiguration in 40 nm","author":"pal","year":"2019","journal-title":"Proc Symp VLSI Technol"},{"key":"ref19","first-page":"1135","article-title":"Learning both weights and connections for efficient neural network","author":"han","year":"0","journal-title":"Proc Adv Neural Inf Process Syst"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2616357"},{"journal-title":"Edge TPU","year":"2019","key":"ref4"},{"journal-title":"Very Deep Convolutional Networks for Large-scale Image Recognition","year":"2014","author":"simonyan","key":"ref27"},{"journal-title":"Neural Compute Stick 2","year":"2019","key":"ref3"},{"journal-title":"Mobilenets Efficient convolutional neural networks for mobile vision applications","year":"2017","author":"howard","key":"ref6"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/5.726791"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1038\/nature16961"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2017.2761740"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2015.7298594"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/3289602.3294007"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2020.2976475"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"436","DOI":"10.1038\/nature14539","article-title":"Deep learning","volume":"521","author":"yann","year":"2015","journal-title":"Nature"},{"journal-title":"SqueezeNet AlexNet-level accuracy with 50x fewer parameters and","year":"2016","author":"iandola","key":"ref20"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2017.643"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/3005348"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR42600.2020.01464"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.2017.7952679"},{"journal-title":"The state of sparsity in deep neural networks","year":"2019","author":"gale","key":"ref41"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-01237-3_12"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/AICAS48895.2020.9073999"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2019.2951121"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001163"}],"container-title":["IEEE Open Journal of Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8784029\/9314963\/09252845.pdf?arnumber=9252845","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,12,17]],"date-time":"2021-12-17T19:58:16Z","timestamp":1639771096000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9252845\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021]]},"references-count":43,"URL":"https:\/\/doi.org\/10.1109\/ojcas.2020.3035402","relation":{},"ISSN":["2644-1225"],"issn-type":[{"type":"electronic","value":"2644-1225"}],"subject":[],"published":{"date-parts":[[2021]]}}}