{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,2]],"date-time":"2026-07-02T22:50:20Z","timestamp":1783032620856,"version":"3.54.6"},"reference-count":54,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2021,1,1]],"date-time":"2021-01-01T00:00:00Z","timestamp":1609459200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/legalcode"}],"funder":[{"DOI":"10.13039\/100006230","name":"Fermilab through DOE","doi-asserted-by":"publisher","award":["DE-AC02-07CH11359"],"award-info":[{"award-number":["DE-AC02-07CH11359"]}],"id":[{"id":"10.13039\/100006230","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000104","name":"NASA Space Technology Research Fellowship","doi-asserted-by":"publisher","award":["80NSSC19K1126"],"award-info":[{"award-number":["80NSSC19K1126"]}],"id":[{"id":"10.13039\/100000104","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Open J. Circuits Syst."],"published-print":{"date-parts":[[2021]]},"DOI":"10.1109\/ojcas.2020.3041208","type":"journal-article","created":{"date-parts":[[2021,1,26]],"date-time":"2021-01-26T20:46:50Z","timestamp":1611694010000},"page":"241-252","source":"Crossref","is-referenced-by-count":27,"title":["A High-Throughput Oversampled Polyphase Filter Bank Using Vivado HLS and PYNQ on a RFSoC"],"prefix":"10.1109","volume":"2","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-0849-5867","authenticated-orcid":false,"given":"Jennifer Pearl","family":"Smith","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4272-263X","authenticated-orcid":false,"given":"J. I.","family":"Bailey","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"John","family":"Tuthill","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Leandro","family":"Stefanazzi","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6926-4010","authenticated-orcid":false,"given":"Gustavo","family":"Cancelo","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ken","family":"Treptow","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Benjamin A.","family":"Mazin","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1007\/s10909-019-02296-2"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/PRIME.2019.8787782"},{"key":"ref33","first-page":"30","article-title":"Xilinx FPGAs beam up next-gen radio astronomy","author":"hampson","year":"2011","journal-title":"Xcell J"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1111\/j.1365-2966.2011.19054.x"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TSP.2013.2295549"},{"key":"ref30","doi-asserted-by":"crossref","first-page":"43","DOI":"10.1117\/12.2314435","article-title":"Highly-multiplexed microwave SQUID readout using the SLAC microresonator radio frequency (SMuRF) electronics for future CMB and sub-millimeter surveys","volume":"10708","author":"henderson","year":"2018","journal-title":"Millimeter Submillimeter and Far-Infrared Detectors and Instrumentation for Astronomy V"},{"key":"ref37","first-page":"1","article-title":"Two FPGA case studies comparing high level synthesis and manual HDL for HEP applications","author":"marc-andr\u00e9","year":"2018","journal-title":"Proc IEEE NPSS Real Time Conf"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1088\/1748-0221\/15\/05\/P05026"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2019.00069"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/3373087.3375332"},{"key":"ref28","author":"harris","year":"2004","journal-title":"Multirate Signal Processing for Communication Systems"},{"key":"ref27","year":"2020","journal-title":"High Throughput Channelizer for FPGA"},{"key":"ref29","article-title":"Digital readout for microwave kinetic inductance detectors and applications in high time resolution astronomy","author":"strader","year":"2016"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MCOM.2016.7378427"},{"key":"ref1","article-title":"Toward 5G Xilinx solutions and enablers for next-generation wireless systems","author":"ahmadi","year":"2016"},{"key":"ref20","first-page":"1","article-title":"Comparison of wideband channelisation architectures","author":"lillington","year":"2003","journal-title":"Proc Int Conf Signal Process"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-12133-3_32"},{"key":"ref21","article-title":"FPGA-based filterbank implementation for parallel digital signal processing","author":"berner","year":"1999"},{"key":"ref24","first-page":"83","article-title":"High performance polyphase FIR filter structures in VHDL language for software defined radio based on FPGA","author":"fiala","year":"2015","journal-title":"Proc Int Conf Appl Electron"},{"key":"ref23","doi-asserted-by":"crossref","first-page":"4","DOI":"10.1016\/S1005-8850(07)60097-8","article-title":"FPGA-based efficient programmable polyphase FIR filter","volume":"14","author":"chen","year":"2005","journal-title":"J Beijing Inst Technol"},{"key":"ref26","article-title":"Polyphase filter bank channelizer","year":"2013"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/NORCHP.2007.4481026"},{"key":"ref50","article-title":"FPGA based polyphase filter bank channelizers","author":"koehn","year":"2014","journal-title":"Proc GNURadio Conf"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1142\/S2251171716410154"},{"key":"ref54","article-title":"Kintex ultraScale FPGAs data sheet: DC and AC switching characteristics","year":"2020"},{"key":"ref53","article-title":"Virtex-6 family overview","year":"2015"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1007\/s10909-020-02463-w"},{"key":"ref10","year":"2020","journal-title":"Vivado High-Level Synthesis"},{"key":"ref11","year":"2020","journal-title":"PYNQ—Python Productivity for Zynq"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1038\/nature02037"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2017.7870368"},{"key":"ref13","article-title":"Integrated SD-FEC in Zynq ultraScale+ RFSoCs for higher throughput and power efficiency (WP498)","author":"finnerty","year":"2018"},{"key":"ref14","article-title":"An adaptable direct RF sampling solution","year":"2019"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2015.2399173"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ACSSC.1989.1200838"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1007\/BF00330404"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TMTT.2003.809176"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/IWCMC48107.2020.9148292"},{"key":"ref4","first-page":"615","author":"pfau","year":"2018","journal-title":"Reconfigurable FPGA-Based Channelization Using Polyphase Filter Banks For Quantum Computing Systems"},{"key":"ref3","article-title":"FPGAs in the emerging DNN inference landscape","year":"2019"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/s10909-018-1981-5"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2019.2920337"},{"key":"ref8","article-title":"FPGA verification challenges and opportunities","author":"foster","year":"2018"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/DSP-SPE.2015.7369562"},{"key":"ref49","first-page":"1","article-title":"Flexible channel extractor For wideband systems based On polyphase filter bank","volume":"95","author":"cappello","year":"2017","journal-title":"J Theor Appl Inf Technol"},{"key":"ref9","author":"bhutani","year":"2019","journal-title":"Field Programmable Gate Array (FPGA) Market Share 2019–2026 Forecasts"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2018.00057"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2020.3008954"},{"key":"ref48","year":"2020","journal-title":"Binary Fixed Point Library for Python"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2018.00089"},{"key":"ref42","article-title":"Zynq ultraScale+ RFSoC RF data converter v2.3 logiCORE IP product guide","year":"2020"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1364\/OE.25.025894"},{"key":"ref44","first-page":"327","year":"2019","journal-title":"Vivado Design Suite Reference Guide Model-Based DSP Design Using System Generator"},{"key":"ref43","article-title":"AXI reference guide","year":"2011"}],"container-title":["IEEE Open Journal of Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8784029\/9314963\/09336352.pdf?arnumber=9336352","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,12,17]],"date-time":"2021-12-17T19:59:06Z","timestamp":1639771146000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9336352\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021]]},"references-count":54,"URL":"https:\/\/doi.org\/10.1109\/ojcas.2020.3041208","relation":{},"ISSN":["2644-1225"],"issn-type":[{"value":"2644-1225","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021]]}}}