{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,24]],"date-time":"2026-03-24T00:46:32Z","timestamp":1774313192668,"version":"3.50.1"},"reference-count":30,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2021,1,1]],"date-time":"2021-01-01T00:00:00Z","timestamp":1609459200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/legalcode"}],"funder":[{"name":"RIE2020 ASTAR AME IAF-ICP","award":["I1801E0030"],"award-info":[{"award-number":["I1801E0030"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Open J. Circuits Syst."],"published-print":{"date-parts":[[2021]]},"DOI":"10.1109\/ojcas.2020.3042550","type":"journal-article","created":{"date-parts":[[2021,1,25]],"date-time":"2021-01-25T22:19:15Z","timestamp":1611613155000},"page":"210-222","source":"Crossref","is-referenced-by-count":26,"title":["A Reconfigurable 4T2R ReRAM Computing In-Memory Macro for Efficient Edge Applications"],"prefix":"10.1109","volume":"2","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-6387-327X","authenticated-orcid":false,"given":"Yuzong","family":"Chen","sequence":"first","affiliation":[]},{"given":"Lu","family":"Lu","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5397-9628","authenticated-orcid":false,"given":"Bongjin","family":"Kim","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1779-1799","authenticated-orcid":false,"given":"Tony Tae-Hyoung","family":"Kim","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref30","author":"chollet","year":"0","journal-title":"Keras Deep Learning for humans"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/CICC48029.2020.9075883"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2019.8824826"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310400"},{"key":"ref13","first-page":"206","article-title":"Liquid silicon: A nonvolatile fully programmable processing-in-memory processor with monolithically integrated ReRAM","author":"zha","year":"2019","journal-title":"Proc IEEE Symp VLSI Circuits"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2018.8614639"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/5.726791"},{"key":"ref16","first-page":"1","article-title":"Low power and high speed bipolar switching with a thin reactive Ti buffer layer in robust HfO? based RRAM","author":"lee","year":"2008","journal-title":"Proc IEEE IEDM"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1002\/adma.200900375"},{"key":"ref18","doi-asserted-by":"crossref","first-page":"35","DOI":"10.1007\/978-3-031-02030-8_4","author":"yu","year":"2016","journal-title":"Resistive Random Access Memory (RRAM) From Devices to Array Architectures"},{"key":"ref19","first-page":"1","article-title":"Bitwise neural networks","author":"kim","year":"2015","journal-title":"Proc Int Conf Mach Learn Workshop Resource-Efficient Mach Learn"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2805470"},{"key":"ref4","doi-asserted-by":"crossref","first-page":"1009","DOI":"10.1109\/JSSC.2016.2515510","article-title":"A 28 nm configurable memory (TCAM\/BCAM\/SRAM) using push-rule 6T bit cell enabling logic-in-memory","volume":"51","author":"jeloka","year":"2016","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/VTSA.2010.5488918"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2012.2190369"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2602218"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2017.2697361"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2316241"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2681458"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2018.8614603"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2017.7870432"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2963616"},{"key":"ref1","first-page":"10","article-title":"Computing’s energy problem (and what we can do about it)","author":"horowitz","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref20","first-page":"1","article-title":"Parallelizing SRAM arrays with customized bit-cell for binary neural networks","author":"liu","year":"2018","journal-title":"Proc ACM\/IEEE Design Autom Conf (DAC)"},{"key":"ref22","first-page":"4107","article-title":"Binarized neural networks","author":"hubara","year":"2016","journal-title":"Proc 30th Conf Neural Inf Process Syst (NIPS)"},{"key":"ref21","author":"lin","year":"2016","journal-title":"Neural networks with few multiplications"},{"key":"ref24","first-page":"120","article-title":"A 5.1 pJ\/neuron 127.3?s\/inference RNN-based speech recognition processor using 16 computing-in-memory SRAM macros in 65 nm CMOS","author":"guo","year":"2019","journal-title":"IEEE Symp VLSI Circuits Dig Tech Papers"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2019.2928043"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2956232"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ICM.2012.6471396"}],"container-title":["IEEE Open Journal of Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8784029\/9314963\/09335229.pdf?arnumber=9335229","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,12,13]],"date-time":"2022-12-13T09:31:43Z","timestamp":1670923903000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9335229\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021]]},"references-count":30,"URL":"https:\/\/doi.org\/10.1109\/ojcas.2020.3042550","relation":{},"ISSN":["2644-1225"],"issn-type":[{"value":"2644-1225","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021]]}}}