{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,6]],"date-time":"2026-04-06T21:11:32Z","timestamp":1775509892556,"version":"3.50.1"},"reference-count":46,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2021,1,1]],"date-time":"2021-01-01T00:00:00Z","timestamp":1609459200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/legalcode"}],"funder":[{"DOI":"10.13039\/501100004721","name":"VLSI Design and Education Center (VDEC), The University of Tokyo, in collaboration with NIHON SYNOPSYS G.K","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100004721","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Renesas Electronics Corp"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Open J. Circuits Syst."],"published-print":{"date-parts":[[2021]]},"DOI":"10.1109\/ojcas.2021.3104945","type":"journal-article","created":{"date-parts":[[2021,8,17]],"date-time":"2021-08-17T20:19:52Z","timestamp":1629231592000},"page":"520-533","source":"Crossref","is-referenced-by-count":8,"title":["Ultralow-Voltage Retention SRAM With a Power Gating Cell Architecture Using Header and Footer Power-Switches"],"prefix":"10.1109","volume":"2","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-4606-7935","authenticated-orcid":false,"given":"Hayato","family":"Yoshida","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3586-9772","authenticated-orcid":false,"given":"Yusaku","family":"Shiotsu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Daiki","family":"Kitagata","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shuu'ichirou","family":"Yamamoto","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Satoshi","family":"Sugahara","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","year":"2021","journal-title":"VLSI Design and Education Center VDEC The University of Tokyo Japan"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2001903"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.891726"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2007.2"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2011972"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2007.4342741"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2100834"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.897148"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2014.2321295"},{"key":"ref34","first-page":"66","article-title":"A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS","author":"jain","year":"2012","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/1165573.1165581"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.1998.672431"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/4.400426"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-0391-0"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/1013235.1013249"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.885057"},{"key":"ref15","first-page":"14","article-title":"Penryn: 45-nm next generation Intel core™ 2 processor","author":"george","year":"2007","journal-title":"Proc IEEE Asian Solid-State Circuits Conf (ASSCC)"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2016.2590142"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1016\/j.mattod.2017.07.007"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2192661"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.7567\/1347-4065\/ab00f5"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/280756.280939"},{"key":"ref4","first-page":"106","article-title":"The implementation of the 65nm dual-core 64b merom processor","author":"sakran","year":"2007","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.1998.687997"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.885041"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2778702"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/.2005.1469239"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIR.2006.307587"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2019.2928043"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2019.2907488"},{"key":"ref2","first-page":"2572","article-title":"A 4.2GHz 0.3mm2 256kb dual-Vcc SRAM building block in 65nm CMOS","author":"khellah","year":"2006","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065653"},{"key":"ref1","author":"harris","year":"2012","journal-title":"Digital Design and computer Architecture"},{"key":"ref46","article-title":"Proposal and performance prediction of a BNN accelerator using ULVR-SRAM","author":"shiotsu","year":"2021","journal-title":"Proc 82nd JSAP Autumn Meeting"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2015.2442980"},{"key":"ref45","first-page":"230","article-title":"A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry","author":"karl","year":"2012","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/S3S.2018.8640173"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/3131848"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2013.6724742"},{"key":"ref24","first-page":"251","article-title":"A pico-joule class, 1 GHz, 32 KJ3yte x 64b DSP SRAM with self reverse bias","author":"bhavnagmala","year":"2003","journal-title":"Proc Symp VLSI Circuits"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.891648"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.807414"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2010.2040664"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.888357"},{"key":"ref43","first-page":"174","article-title":"A 0.45-1V fully integrated reconfigurable switched capacitor step-down DC–DC converter with high density MIM capacitor in 22nm tri-gate CMOS","author":"jain","year":"2013","journal-title":"Proc Symp VLSI Circuits"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/SOC.2003.1241450"}],"container-title":["IEEE Open Journal of Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8784029\/9314963\/09515125.pdf?arnumber=9515125","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,12,17]],"date-time":"2021-12-17T19:59:09Z","timestamp":1639771149000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9515125\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021]]},"references-count":46,"URL":"https:\/\/doi.org\/10.1109\/ojcas.2021.3104945","relation":{},"ISSN":["2644-1225"],"issn-type":[{"value":"2644-1225","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021]]}}}