{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,10]],"date-time":"2026-02-10T16:16:58Z","timestamp":1770740218309,"version":"3.49.0"},"reference-count":27,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2026,1,1]],"date-time":"2026-01-01T00:00:00Z","timestamp":1767225600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/legalcode"}],"funder":[{"DOI":"10.13039\/501100003005","name":"Technische Universiteit Eindhoven","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100003005","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Open J. Circuits Syst."],"published-print":{"date-parts":[[2026]]},"DOI":"10.1109\/ojcas.2026.3655136","type":"journal-article","created":{"date-parts":[[2026,1,19]],"date-time":"2026-01-19T20:57:34Z","timestamp":1768856254000},"page":"21-32","source":"Crossref","is-referenced-by-count":0,"title":["Spur Analysis and Linearity Enhancement in Fractional-N Phase Locked Loops Through Parallel Sigma\u2013Delta Modulators With Time Offsets"],"prefix":"10.1109","volume":"7","author":[{"ORCID":"https:\/\/orcid.org\/0009-0004-8505-5648","authenticated-orcid":false,"given":"Johan","family":"Holmstedt","sequence":"first","affiliation":[{"name":"Department of Electrical Engineering, Eindhoven University of Technology, Eindhoven, The Netherlands"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6836-0641","authenticated-orcid":false,"given":"Henrik","family":"Sj\u00f6land","sequence":"additional","affiliation":[{"name":"Department of Electrical and Information Technology, Lund University, Lund, Sweden"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2021.3111430"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2021.3057580"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2899726"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3123827"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC49661.2025.10904710"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2314436"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2596766"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2022.3141782"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2023.3311681"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9062948"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2022.3195659"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2414421"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2024.3501196"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2024.3469556"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/RFIC.2018.8428999"},{"key":"ref16","volume-title":"Differential digital-to-time converter for even-order INL cancellation and supply noise\/disturbance rejection","author":"Li","year":"2022"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2024.3477498"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2022.3209614"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC49661.2025.10904516"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2290298"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3111134"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2022.3200475"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2025.3548028"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42615.2023.10067351"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2025.3560870"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2019.2925181"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2021.3063206"}],"container-title":["IEEE Open Journal of Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/8784029\/11367652\/11357518.pdf?arnumber=11357518","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,2,9]],"date-time":"2026-02-09T21:10:50Z","timestamp":1770671450000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11357518\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026]]},"references-count":27,"URL":"https:\/\/doi.org\/10.1109\/ojcas.2026.3655136","relation":{},"ISSN":["2644-1225"],"issn-type":[{"value":"2644-1225","type":"electronic"}],"subject":[],"published":{"date-parts":[[2026]]}}}