{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,24]],"date-time":"2024-10-24T04:24:11Z","timestamp":1729743851110,"version":"3.28.0"},"reference-count":7,"publisher":"IEEE","license":[{"start":{"date-parts":[[2002,1,1]],"date-time":"2002-01-01T00:00:00Z","timestamp":1009843200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2002,1,1]],"date-time":"2002-01-01T00:00:00Z","timestamp":1009843200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2002]]},"DOI":"10.1109\/olt.2002.1030193","type":"proceedings-article","created":{"date-parts":[[2003,6,25]],"date-time":"2003-06-25T22:14:31Z","timestamp":1056579271000},"page":"112-116","source":"Crossref","is-referenced-by-count":20,"title":["Analysis of SEU effects in a pipelined processor"],"prefix":"10.1109","author":[{"given":"M.","family":"Rebaudengo","sequence":"first","affiliation":[{"name":"Dipt. di Automatica e Informatica, Politecnico di Torino, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Sonza Reorda","sequence":"additional","affiliation":[{"name":"Dipt. di Automatica e Informatica, Politecnico di Torino, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Violante","sequence":"additional","affiliation":[{"name":"Dipt. di Automatica e Informatica, Politecnico di Torino, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","first-page":"140","article-title":"A Study of the Experimental Validation of Fault-Tolerant Systems using different VHDL-Based Fault Injection Techniques","author":"garcia","year":"2000","journal-title":"IEEE International On-Line Test Workshop"},{"key":"ref3","first-page":"61","article-title":"New Techniques for Accelerating Fault Injection in VHDL descriptions","author":"parrotta","year":"2000","journal-title":"IEEE International On-Line Test Workshop"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.1109\/VTEST.1999.766651"},{"doi-asserted-by":"publisher","key":"ref5","DOI":"10.1109\/ATS.2001.990301"},{"year":"0","key":"ref7"},{"key":"ref2","article-title":"Experimental Analysis of Computer System Dependability","author":"iyer","year":"1996","journal-title":"Chapter 5 of Fault-Tolerant Computer System Design"},{"doi-asserted-by":"publisher","key":"ref1","DOI":"10.1109\/23.903784"}],"event":{"name":"Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW 2002)","start":{"date-parts":[[2002,7,10]]},"location":"Bendor, France","end":{"date-parts":[[2002,7,10]]}},"container-title":["Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW 2002)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8008\/22136\/01030193.pdf?arnumber=1030193","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T17:46:15Z","timestamp":1729705575000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/1030193\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2002]]},"references-count":7,"URL":"https:\/\/doi.org\/10.1109\/olt.2002.1030193","relation":{},"subject":[],"published":{"date-parts":[[2002]]}}}