{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T03:03:32Z","timestamp":1725419012976},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/olt.2002.1030229","type":"proceedings-article","created":{"date-parts":[[2003,6,25]],"date-time":"2003-06-25T18:14:31Z","timestamp":1056564871000},"page":"262-267","source":"Crossref","is-referenced-by-count":3,"title":["A simulator for evaluating redundancy analysis algorithms of repairable embedded memories"],"prefix":"10.1109","author":[{"family":"Rei-Fu Huang","sequence":"first","affiliation":[]},{"family":"Jin-Fu Li","sequence":"additional","affiliation":[]},{"family":"Jen-Chieh Yeh","sequence":"additional","affiliation":[]},{"family":"Cheng-Wen Wu","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2000.894250"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/43.46807"},{"journal-title":"Testing Semiconductor Memories Theory and Practice","year":"1998","author":"van de goor","key":"ref10"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2001.966632"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2000.893601"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.1987.295111"},{"key":"ref12","first-page":"468","article-title":"Error catch and analysis for semiconductor memories using March tests","author":"wu","year":"2000","journal-title":"Proc IEEE IACM Int Con! Computer-Aided Design (ICCAD)"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/MTDT.2001.945228"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1999.805644"},{"journal-title":"Essentials of Electronic Testing for Digital Memory and Mixed-Signal VLSI Circuits","year":"2000","author":"bushnell","key":"ref2"},{"key":"ref9","first-page":"175","article-title":"Defect analysis system speeds test and repair of redundant memories","author":"tarr","year":"1984","journal-title":"Electronics"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1999.805645"}],"event":{"name":"Eighth IEEE International On-Line Testing Workshop (IOLTW 2002)","acronym":"OLT-02","location":"Isle of Bendor, France"},"container-title":["Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW 2002)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8008\/22136\/01030229.pdf?arnumber=1030229","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,10]],"date-time":"2017-03-10T16:41:17Z","timestamp":1489164077000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1030229\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/olt.2002.1030229","relation":{},"subject":[]}}