{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T07:50:20Z","timestamp":1725522620912},"reference-count":18,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,8]]},"DOI":"10.1109\/pacrim.2017.8121912","type":"proceedings-article","created":{"date-parts":[[2017,11,30]],"date-time":"2017-11-30T16:59:14Z","timestamp":1512061154000},"page":"1-6","source":"Crossref","is-referenced-by-count":1,"title":["Initial study of a phase-aware scheduling for hardware transactional memory"],"prefix":"10.1109","author":[{"given":"Tomoki","family":"Tajimi","sequence":"first","affiliation":[]},{"given":"Anju","family":"Hirota","sequence":"additional","affiliation":[]},{"given":"Ryota","family":"Shioya","sequence":"additional","affiliation":[]},{"given":"Masahiro","family":"Goshima","sequence":"additional","affiliation":[]},{"given":"Tomoaki","family":"Tsumura","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","article-title":"STAMP: Stanford Transactional Applications for Multi-Processing","author":"minh","year":"2008","journal-title":"Proc IEEE Int'l Symp On Workload Characterization (IISWC'08)"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2003.1183520"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.17"},{"key":"ref13","doi-asserted-by":"crossref","first-page":"145","DOI":"10.1145\/1669112.1669132","article-title":"Eazyhtm, Eager-lazy Hardware Transactional Memory","author":"tomic","year":"2009","journal-title":"Proc 42nd Annu IEEE\/ACM Int Symp Microarch (MICRO-42)"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.23"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/1378533.1378564"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2011.5749718"},{"key":"ref17","article-title":"A Comprehensive Study of Conflict Resolution Policies in Hardware Transactional Memory","author":"akpinar","year":"2011","journal-title":"Proc 6th ACM SIGPLAN Workshop on Transactional Computing (TRANSACT'11)"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/HiPC.2013.6799100"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1587\/transinf.2016PAP0006"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/CANDAR.2016.0026"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/2.982916"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/123465.123475"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346204"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/1105734.1105747"},{"journal-title":"Power ISA® Version 2 07","year":"2013","key":"ref2"},{"journal-title":"Intel Architecture Instruction Set Extensions Programming Reference","article-title":"Intel Corporation","year":"2012","key":"ref1"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1995.524546"}],"event":{"name":"2017 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM)","start":{"date-parts":[[2017,8,21]]},"location":"Victoria, BC","end":{"date-parts":[[2017,8,23]]}},"container-title":["2017 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8116603\/8121873\/08121912.pdf?arnumber=8121912","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,10,7]],"date-time":"2019-10-07T01:30:34Z","timestamp":1570411834000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8121912\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,8]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/pacrim.2017.8121912","relation":{},"subject":[],"published":{"date-parts":[[2017,8]]}}}