{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T02:08:30Z","timestamp":1725674910863},"reference-count":13,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/pact.2002.1106021","type":"proceedings-article","created":{"date-parts":[[2003,6,25]],"date-time":"2003-06-25T20:51:07Z","timestamp":1056574267000},"page":"232-241","source":"Crossref","is-referenced-by-count":4,"title":["Cost effective memory dependence prediction using speculation levels and color sets"],"prefix":"10.1109","author":[{"given":"S.","family":"Onder","sequence":"first","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1999.809454"},{"key":"ref11","article-title":"Dynamic memory disambiguation in the presence of out-of-order store issuing","author":"onder","year":"2002","journal-title":"Journal of Instruction Level Parallelism"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1998.742775"},{"article-title":"Memory reference tagging","year":"1994","author":"steely","key":"ref13"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1998.694768"},{"key":"ref3","first-page":"245","article-title":"Two techniques to enhance the performance of memory consistency models","author":"gharachorloo","year":"1991","journal-title":"Proceedings of the International Conference on Parallel Processing"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1996.566457"},{"article-title":"Apparatus to dynamically control the Out-Of-Order execution of Load-Store instructions","year":"1995","author":"hesson","key":"ref5"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1997.604684"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1998.727028"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1998.694770"},{"key":"ref1","article-title":"A comparative survey of load speculation architectures","author":"calder","year":"2000","journal-title":"Journal of Instruction Level Parallelism"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ICCL.1998.674159"}],"event":{"name":"2002 International Conference on Parallel Architectures and Compilation Techniques. PACT 2002","acronym":"PACT-02","location":"Charlottesville, VA, USA"},"container-title":["Proceedings.International Conference on Parallel Architectures and Compilation Techniques"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8167\/24312\/01106021.pdf?arnumber=1106021","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,13]],"date-time":"2017-03-13T17:54:00Z","timestamp":1489427640000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1106021\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/pact.2002.1106021","relation":{},"subject":[]}}