{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T11:43:51Z","timestamp":1742384631392,"version":"3.28.0"},"reference-count":38,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/pact.2002.1106027","type":"proceedings-article","created":{"date-parts":[[2003,6,25]],"date-time":"2003-06-25T20:51:07Z","timestamp":1056574267000},"page":"281-290","source":"Crossref","is-referenced-by-count":11,"title":["Exploiting pseudo-schedules to guide data dependence graph partitioning"],"prefix":"10.1109","author":[{"given":"A.","family":"Aleta","sequence":"first","affiliation":[]},{"given":"J.M.","family":"Codina","sequence":"additional","affiliation":[]},{"given":"J.","family":"Sanchez","sequence":"additional","affiliation":[]},{"given":"A.","family":"Gonzalez","sequence":"additional","affiliation":[]},{"given":"D.","family":"Kaeli","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref38","doi-asserted-by":"crossref","DOI":"10.1109\/MICRO.2001.991115","article-title":"Modulo Scheduling with Integrated Register Spilling for Clustered VLIW Architectures","author":"zalamea","year":"2001","journal-title":"Proc 34th Int l Symp Microarchitecture"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1145\/1014192.802449"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/192724.192731"},{"key":"ref31","first-page":"348","article-title":"The ManArray Embedded Processor Architecture","author":"pechanek","year":"2000","journal-title":"Proc 26th Euromicro Conf"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1998.742792"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1145\/349299.349319"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/ICPP.2000.876173"},{"key":"ref35","doi-asserted-by":"crossref","first-page":"124","DOI":"10.1109\/MICRO.2000.898064","article-title":"Modulo Scheduling for a Fully-Distributed Clustered VLIW Architecture","author":"s\u00e1nchez","year":"2000","journal-title":"Proc 33rd Int'l Symp Microarchitecture"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1997.645831"},{"article-title":"Bulldog: A Compiler for VLIW Architecture","year":"1986","author":"ellis","key":"ref10"},{"key":"ref11","first-page":"203","article-title":"Lx: a technology platform for customizable VLIW embedded processing","author":"faraboschi","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/IPPS.1998.669945"},{"key":"ref13","first-page":"175","article-title":"A Linear-Time Heuristic for Improving Network Partitions","author":"fiduccia","year":"1982","journal-title":"Proc of 19th Design Automation Conference"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/40.820055"},{"article-title":"Implementation of Algorithms for Maximum Matching on Nonbipartite Graphs","year":"1973","author":"gabow","key":"ref15"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/514191.514222"},{"key":"ref17","article-title":"A Multi-Level Algorithm For Partitioning Graphs","author":"hendrickson","year":"1995","journal-title":"Supercomputing"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/5.920580"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/155090.155115"},{"journal-title":"Algorithmic Solutions Software GmbH","article-title":"Maximum Weighted Matching in General Graphs","year":"2001","key":"ref28"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/C-M.1981.220595"},{"key":"ref27","article-title":"MAP1000. MAP1000 unfolds at Equator","volume":"12","year":"1998","journal-title":"Microprocessor Report"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1992.697033"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2001.953298"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1998.742773"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/514191.514208"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1995.476843"},{"key":"ref7","article-title":"Instruction Assignment for Clustered VLIW DSP Compilers","author":"desoli","year":"1998","journal-title":"Technical Report HP-98&#x2013;13 HP Labs Technical Report"},{"key":"ref2","article-title":"Ictineo: A Tool for Research on IL P","author":"ayguad\u00e9","year":"1996","journal-title":"Supercomputing 96"},{"key":"ref9","article-title":"Optimum Module Schedules for Minimum Register Requirements","author":"eichenberger","year":"1995","journal-title":"Proc of Supercomputing &#x2018;95"},{"key":"ref1","doi-asserted-by":"crossref","DOI":"10.1109\/MICRO.2001.991114","article-title":"Graph-Partitioning Based Instruction Scheduling for Clustered Processors","author":"alet\u00e0","year":"2001","journal-title":"Proc 34th Int l Symp Microarchitecture"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/113445.113464"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2001.903258"},{"key":"ref21","article-title":"A Code Generation Framework for VLIW Architectures","author":"jang","year":"1998","journal-title":"Proc of the 3rd Int Conf on Massively Parallel Computing Systems"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/53990.54022"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1002\/j.1538-7305.1970.tb01770.x"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/12.689643"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/12.910814"}],"event":{"name":"2002 International Conference on Parallel Architectures and Compilation Techniques. PACT 2002","acronym":"PACT-02","location":"Charlottesville, VA, USA"},"container-title":["Proceedings.International Conference on Parallel Architectures and Compilation Techniques"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8167\/24312\/01106027.pdf?arnumber=1106027","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,15]],"date-time":"2017-06-15T18:45:39Z","timestamp":1497552339000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1106027\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":38,"URL":"https:\/\/doi.org\/10.1109\/pact.2002.1106027","relation":{},"subject":[]}}