{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T11:14:03Z","timestamp":1742382843813,"version":"3.28.0"},"reference-count":27,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/pact.2002.1106028","type":"proceedings-article","created":{"date-parts":[[2003,6,25]],"date-time":"2003-06-25T20:51:07Z","timestamp":1056574267000},"page":"291-300","source":"Crossref","is-referenced-by-count":24,"title":["Efficient interconnects for clustered microarchitectures"],"prefix":"10.1109","author":[{"given":"J.-M.","family":"Parcerisa","sequence":"first","affiliation":[]},{"given":"J.","family":"Sahuquillo","sequence":"additional","affiliation":[]},{"given":"A.","family":"Gonzalez","sequence":"additional","affiliation":[]},{"given":"J.","family":"Duato","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","article-title":"Digital 21264 Sets New Standard","volume":"10","author":"gwennap","year":"1996","journal-title":"Microprocessor Report"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/5.920580"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ICPP.1996.537165"},{"key":"ref13","first-page":"1","article-title":"Intel Embraces Multithreading","author":"krewell","year":"2001","journal-title":"Microprocessor Report"},{"journal-title":"The International Technology Roadmap for Semiconductors","year":"1999","key":"ref14"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1997.645830"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/2.612245"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1997.604689"},{"article-title":"Complexity-Effective Superscalar Processors","year":"1998","author":"palacharla","key":"ref18"},{"key":"ref19","doi-asserted-by":"crossref","first-page":"317","DOI":"10.1109\/MICRO.2000.898081","article-title":"Reducing Wire Delay Penalty through Value Prediction","author":"parcerisa","year":"2000","journal-title":"Proc 33rd Int l Symp Microarchitecture (MICRO-33)"},{"key":"ref4","article-title":"Evaluating Future Microprocessors: The SimpleScalar Tool Set","author":"burger","year":"1996","journal-title":"Tech Report CS-TR-96&#x2013;1308"},{"journal-title":"Inherently Lower-Power High-Performance Superscalar Architectures","year":"2000","author":"zyuban","key":"ref27"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.1995.499187"},{"key":"ref6","first-page":"132","article-title":"Dynamic Cluster Assignment Mechanisms","author":"canal","year":"2000","journal-title":"Proc Int l Symp High-Performance Computer Architecture"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.1999.807517"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1997.645806"},{"journal-title":"Interconnection Networks An Engineering Approach","year":"1997","author":"duato","key":"ref7"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"337","DOI":"10.1109\/MICRO.2000.898083","article-title":"Instruction Distribution Heuristics for Quad-Cluster, Dynamically-Scheduled, Superscalar Processors","author":"baniasadi","year":"2000","journal-title":"Proc 33 rd Int'l Symp on Microarchitecture (MICRO-33)"},{"journal-title":"The Multiscalar Architecture","year":"1993","author":"franklin","key":"ref9"},{"key":"ref1","first-page":"248","article-title":"Clock rate versus IPC: the end of the road for conventional microarchitectures","author":"agarwal","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"ref20","article-title":"Building Fully Distributed Microarchitectures with Processor Slices","author":"parcerisa","year":"2001","journal-title":"tech report UPC-DAC-2001&#x2013;33"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1997.645805"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/291069.291061"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/40.888700"},{"key":"ref23","article-title":"POWER4 System Microarchitecture","author":"tendler","year":"2001","journal-title":"Technical White Paper"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/40.491460"},{"key":"ref25","doi-asserted-by":"crossref","first-page":"35","DOI":"10.1109\/PACT.1996.552553","article-title":"The Superthreaded Architecture: Thread Pipelining with Run-Time Data Dependence Checking and Control Speculation","author":"tsai","year":"1996","journal-title":"Proc Int'l Conf on Parallel Architectures and Compilation Techniques"}],"event":{"name":"2002 International Conference on Parallel Architectures and Compilation Techniques. PACT 2002","acronym":"PACT-02","location":"Charlottesville, VA, USA"},"container-title":["Proceedings.International Conference on Parallel Architectures and Compilation Techniques"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8167\/24312\/01106028.pdf?arnumber=1106028","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,15]],"date-time":"2017-06-15T18:45:39Z","timestamp":1497552339000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1106028\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":27,"URL":"https:\/\/doi.org\/10.1109\/pact.2002.1106028","relation":{},"subject":[]}}