{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T06:54:23Z","timestamp":1747810463205,"version":"3.28.0"},"reference-count":16,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/pact.2003.1238016","type":"proceedings-article","created":{"date-parts":[[2004,3,22]],"date-time":"2004-03-22T09:34:28Z","timestamp":1079948068000},"page":"206-216","source":"Crossref","is-referenced-by-count":4,"title":["Memory hierarchy design for a multiprocessor look-up engine"],"prefix":"10.1109","author":[{"given":"J.-L.","family":"Baer","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"D.","family":"Low","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"P.","family":"Crowley","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"N.","family":"Sidhwaney","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/49.772439"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/40.917999"},{"journal-title":"Computer Networks A systems approach-2nd Ed","year":"2000","author":"peterson","key":"ref12"},{"key":"ref13","article-title":"Suporting network algorithms with a pipelined architecture","author":"sherwood","year":"2003","journal-title":"Proc of ISCA 2003"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/35.668285"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/296502.296503"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/502912.502914"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/40.903060"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/335231.335237"},{"key":"ref6","volume":"3","author":"knuth","year":"1973","journal-title":"The art of computer programming"},{"journal-title":"The role of network processors in next generation networks","year":"2001","key":"ref5"},{"journal-title":"IPMA reports","year":"2002","key":"ref8"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1016\/B978-155860875-7\/50029-6"},{"key":"ref2","first-page":"409","article-title":"Cache memory design for network processors","author":"chiueh","year":"2000","journal-title":"Proc 6th Int Symp High-Performance Comput Architec"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/INFCOM.1999.752162"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/378420.378423"}],"event":{"name":"12th International Conference on Parallel Architectures and Compilation Techniques. PACT 2003","acronym":"PACT-03","location":"New Orleans, LA, USA"},"container-title":["Oceans 2002 Conference and Exhibition. Conference Proceedings (Cat. No.02CH37362)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8771\/27774\/01238016.pdf?arnumber=1238016","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,13]],"date-time":"2017-03-13T21:06:37Z","timestamp":1489439197000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1238016\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/pact.2003.1238016","relation":{},"subject":[]}}