{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,4]],"date-time":"2025-06-04T01:09:18Z","timestamp":1748999358360,"version":"3.28.0"},"reference-count":26,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/pact.2003.1238021","type":"proceedings-article","created":{"date-parts":[[2004,3,22]],"date-time":"2004-03-22T09:34:28Z","timestamp":1079948068000},"page":"258-268","source":"Crossref","is-referenced-by-count":13,"title":["Reducing datapath energy through the isolation of short-lived operands"],"prefix":"10.1109","author":[{"given":"D.","family":"Ponomarev","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"G.","family":"Kucuk","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"O.","family":"Ergin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"K.","family":"Ghose","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"Intel Corporation","article-title":"The Intel Architecture Software Developers Manual","year":"1999","key":"ref10"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/40.755465"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/514191.514202"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1995.476839"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2002.1176234"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1993.282742"},{"key":"ref16","article-title":"AMD's K5 Designed to Outrun Pentium","volume":"8","author":"slater","year":"1994","journal-title":"Microprocessor Report"},{"key":"ref17","article-title":"Lazy Retirement: A Power Aware Register Management Mechanism","author":"savransky","year":"2002","journal-title":"Workshop on Complexity-Effective Design"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/MM.1994.363071"},{"key":"ref19","doi-asserted-by":"crossref","first-page":"36","DOI":"10.1145\/327070.327125","article-title":"Implementation of Precise Interrupts in Pipelined Processors","author":"smith","year":"1985","journal-title":"Proceedings of International Symposium on Computer Architecture"},{"key":"ref4","first-page":"316","article-title":"Multiple-banked register file architectures","author":"cruz","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"ref3","article-title":"Loose Loops Sink Chips”, in Proceedings of Int'l","author":"borch","year":"2002","journal-title":"Conference on High Performance Computer Architecture (HPCA-02)"},{"key":"ref6","doi-asserted-by":"crossref","DOI":"10.1145\/384285.379266","article-title":"Energy-Effective IssueLogic","author":"folegnani","year":"2001","journal-title":"Proc Int Symp Computer Architecture"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2002.1106757"},{"key":"ref8","article-title":"PA-8000 Combines Complexity and Speed","volume":"8","author":"gwennap","year":"1994","journal-title":"Microprocessor Report"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1992.697025"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2001.991122"},{"key":"ref9","article-title":"Reducing Register File Power Consumption by Exploiting Value Lifetime Characteristics","author":"hu","year":"2000","journal-title":"Workshop on Complexity-Effective Design"},{"key":"ref1","article-title":"The SimpleScalartool set: Version 2.0","author":"burger","year":"0","journal-title":"Tech Report Dept of CS Univ of Wisconsin-Madison June 1997 and documentation for all Simplescalar releases (through version 3 0)"},{"key":"ref20","article-title":"Banked Multi-ported Register Files for High Frequency Superscalar Microprocessors","author":"tseng","year":"2003","journal-title":"Proc of ISCA"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2002.1176248"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.1996.552666"},{"key":"ref24","article-title":"Managing the Impact of Increasing Microprocessor Power Consumption","author":"gunther","year":"2001","journal-title":"Intel Technology Journal Ql"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/782837.782839"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/871506.871564"},{"key":"ref25","first-page":"41","article-title":"Shrinking Devices Put a Squeeze on System Packaging","volume":"39","author":"small","year":"1994","journal-title":"EDN"}],"event":{"name":"12th International Conference on Parallel Architectures and Compilation Techniques. PACT 2003","acronym":"PACT-03","location":"New Orleans, LA, USA"},"container-title":["Oceans 2002 Conference and Exhibition. Conference Proceedings (Cat. No.02CH37362)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8771\/27774\/01238021.pdf?arnumber=1238021","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,16]],"date-time":"2017-06-16T00:26:35Z","timestamp":1497572795000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1238021\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":26,"URL":"https:\/\/doi.org\/10.1109\/pact.2003.1238021","relation":{},"subject":[]}}