{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,5]],"date-time":"2025-11-05T06:20:45Z","timestamp":1762323645877},"reference-count":20,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,10]]},"DOI":"10.1109\/pact.2013.6618803","type":"proceedings-article","created":{"date-parts":[[2013,10,10]],"date-time":"2013-10-10T19:35:09Z","timestamp":1381433709000},"page":"123-132","source":"Crossref","is-referenced-by-count":11,"title":["L1-bandwidth aware thread allocation in multicore SMT processors"],"prefix":"10.1109","author":[{"given":"Hiroshi","family":"Sasaki","sequence":"first","affiliation":[]},{"given":"Satoshi","family":"Imamura","sequence":"additional","affiliation":[]},{"given":"Koji","family":"Inoue","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"WT1600 Digital Power Meter","year":"0","key":"19"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1145\/378993.379244"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1145\/1854273.1854283"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000117"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1145\/2370816.2370833"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2006.1598114"},{"key":"14","first-page":"164","article-title":"Balancing thoughput and fairness in SMT processors","author":"lun","year":"2001","journal-title":"ISPASS '01"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1145\/1807128.1807136"},{"key":"12","first-page":"123","article-title":"System level analysis of fast, per-core DVFS using on-chip switching regulators","author":"kim","year":"2008","journal-title":"HPCA '08"},{"journal-title":"Benchmarking Modern Multiprocessors","year":"2011","author":"bienia","key":"3"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1145\/1736020.1736036"},{"key":"2","first-page":"189","article-title":"An approach to resource-aware coscheduling for CMPs","author":"bhadauria","year":"2010","journal-title":"10th ICSE"},{"key":"1","article-title":"AMD'Bulldozer' core technology","author":"micro devices","year":"2011","journal-title":"Advanced Micro Devices White Paper"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.8"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250665"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.44"},{"key":"5","first-page":"365","article-title":"Dark silicon and the end of multicore scaling","author":"esmaeilzadeh","year":"2011","journal-title":"2011 38th Annual International Symposium on Computer Architecture (ISCA) ISCA"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155641"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1088\/1742-6596\/46\/1\/067"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2007.4336197"}],"event":{"name":"22nd International Conference on Parallel Architectures and Compilation Techniques (PACT)","start":{"date-parts":[[2013,9,7]]},"location":"Edinburgh","end":{"date-parts":[[2013,9,11]]}},"container-title":["Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6603429\/6618788\/06618803.pdf?arnumber=6618803","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,22]],"date-time":"2017-03-22T13:05:37Z","timestamp":1490187937000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6618803\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,10]]},"references-count":20,"URL":"https:\/\/doi.org\/10.1109\/pact.2013.6618803","relation":{},"subject":[],"published":{"date-parts":[[2013,10]]}}}