{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,21]],"date-time":"2026-02-21T18:18:39Z","timestamp":1771697919538,"version":"3.50.1"},"reference-count":25,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,10]]},"DOI":"10.1109\/pact.2013.6618810","type":"proceedings-article","created":{"date-parts":[[2013,10,10]],"date-time":"2013-10-10T23:35:09Z","timestamp":1381448109000},"page":"201-212","source":"Crossref","is-referenced-by-count":3,"title":["An empirical model for predicting cross-core performance interference on multicore processors"],"prefix":"10.1109","author":[{"given":"Josue","family":"Feliu","sequence":"first","affiliation":[]},{"given":"Julio","family":"Sahuquillo","sequence":"additional","affiliation":[]},{"given":"Salvador","family":"Petit","sequence":"additional","affiliation":[]},{"given":"Jose","family":"Duato","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669177"},{"key":"17","first-page":"3","article-title":"Transactions on high-performance embedded architectures and compilers III","author":"moreto","year":"2011","journal-title":"Dynamic Cache Partitioning Based on the MLP of Cache Misses"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1145\/1787275.1787320"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.25"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454148"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/ICPPW.2010.53"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2004.17"},{"key":"11","first-page":"481","article-title":"Characterizing the resource-sharing levels in the ultrasparc t2 processor","author":"akarevic?","year":"2009","journal-title":"International Symposium on Microarchitecture (MICRO)"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/SBAC-PAD.2009.13"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1145\/1995896.1995927"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2012.6237037"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771801"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1145\/1353522.1353531"},{"key":"24","doi-asserted-by":"crossref","DOI":"10.1145\/356989.357011","article-title":"Symbiotic jobscheduling for a simultaneous mutlithreading processor","volume":"35","author":"snavely","year":"2000","journal-title":"SIGPLAN Not"},{"key":"25","first-page":"164","article-title":"Balancing thoughput and fairness in SMT processors","author":"luo","year":"2001","journal-title":"International Symposium on Performance Analysis of Systems and Software (ISPASS)"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1145\/1854273.1854306"},{"key":"2","first-page":"286","article-title":"Realistic workload scheduling policies for taming the memory bandwidth bottleneck of smps","author":"antonopoulos","year":"2004","journal-title":"High Performance Computing (HiPC)"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1145\/1736020.1736033"},{"key":"1","first-page":"392","article-title":"Simultaneous multithreading: Maximizing on-chip parallelism","author":"tullsen","year":"1995","journal-title":"Proceedings 22nd Annual International Symposium on Computer Architecture ISCA"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.48"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2012.54"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1145\/1736020.1736036"},{"key":"4","first-page":"283","article-title":"The impact of memory subsystem resource sharing on datacenter applications","author":"lingjia tang","year":"2011","journal-title":"2011 38th Annual International Symposium on Computer Architecture (ISCA) ISCA"},{"key":"9","doi-asserted-by":"crossref","first-page":"201","DOI":"10.1007\/978-3-642-11515-8_16","article-title":"Combining locality analysis with online proactive job co-scheduling in chip multiprocessors","author":"jiang","year":"2010","journal-title":"International Conference on High Performance Embedded Architectures and Compilers (HiPEAC)"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2007.4336197"}],"event":{"name":"22nd International Conference on Parallel Architectures and Compilation Techniques (PACT)","location":"Edinburgh","start":{"date-parts":[[2013,9,7]]},"end":{"date-parts":[[2013,9,11]]}},"container-title":["Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6603429\/6618788\/06618810.pdf?arnumber=6618810","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,21]],"date-time":"2017-06-21T23:30:15Z","timestamp":1498087815000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6618810\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,10]]},"references-count":25,"URL":"https:\/\/doi.org\/10.1109\/pact.2013.6618810","relation":{},"subject":[],"published":{"date-parts":[[2013,10]]}}}