{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,18]],"date-time":"2025-10-18T10:35:33Z","timestamp":1760783733738},"reference-count":27,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,10]]},"DOI":"10.1109\/pact.2013.6618819","type":"proceedings-article","created":{"date-parts":[[2013,10,10]],"date-time":"2013-10-10T19:35:09Z","timestamp":1381433709000},"page":"299-308","source":"Crossref","is-referenced-by-count":6,"title":["Building expressive, area-efficient coherence directories"],"prefix":"10.1109","author":[{"given":"Vineeth","family":"Mekkat","sequence":"first","affiliation":[]},{"given":"Anup","family":"Holey","sequence":"additional","affiliation":[]},{"family":"Pen-Chung Yew","sequence":"additional","affiliation":[]},{"given":"Antonia","family":"Zhai","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250709"},{"journal-title":"NVIDIA CUDA C Programming Guide","year":"0","key":"17"},{"journal-title":"Nvidia Project Denver","year":"0","key":"18"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771793"},{"key":"16","article-title":"Mlpaware dynamic cache partitioning","author":"moreto","year":"2008","journal-title":"HiPEAC"},{"key":"13","article-title":"TAP: A TLP-aware cache management policy for a CPU-GPU heterogeneous architecture","author":"lee","year":"2012","journal-title":"HPCA"},{"key":"14","article-title":"Mcpat: An integrated power, area, and timing modeling framework for multicore and manycore architectures","author":"li","year":"2009","journal-title":"Micro"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2004.1342546"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1145\/379240.379259"},{"key":"21","article-title":"Utility-based cache partitioning: A low-overhead, high-performance, runtime mechanism to partition shared caches","author":"qureshi","year":"2006","journal-title":"Micro"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.5"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2008.4658623"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1145\/1241601.1241625"},{"key":"24","doi-asserted-by":"publisher","DOI":"10.1023\/B:SUPE.0000014800.27383.8f"},{"key":"25","doi-asserted-by":"publisher","DOI":"10.1145\/2370816.2370865"},{"key":"26","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555778"},{"key":"27","article-title":"Scalable shared-cache management by containing thrashing workloads","author":"xie","year":"2010","journal-title":"HiPEAC"},{"key":"3","article-title":"AMD fusion family of APUs: Enabling a superior, immersive pc experience","author":"brookwood","year":"2010","journal-title":"AMD White Paper"},{"year":"0","key":"2"},{"journal-title":"OpenCL-The Open Standard for Parallel Programming of Heterogeneous Systems","year":"0","key":"10"},{"journal-title":"AMD Accelerated Parallel Processing (APP) Software Development Kit (SDK)","year":"0","key":"1"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/12.817393"},{"key":"6","article-title":"High performance cache replacement using re-reference interval prediction (RRIP)","author":"jaleel","year":"2010","journal-title":"ISCA"},{"journal-title":"Intel Sandy Bridge Microarchitecture","year":"0","key":"5"},{"key":"4","article-title":"Simpoint 3. 0: Faster and more flexible program analysis","author":"hamerly","year":"2005","journal-title":"Journal of Instruction Level Parallelism"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2007.70816"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.24"}],"event":{"name":"22nd International Conference on Parallel Architectures and Compilation Techniques (PACT)","start":{"date-parts":[[2013,9,7]]},"location":"Edinburgh","end":{"date-parts":[[2013,9,11]]}},"container-title":["Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6603429\/6618788\/06618819.pdf?arnumber=6618819","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,22]],"date-time":"2017-03-22T13:01:54Z","timestamp":1490187714000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6618819\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,10]]},"references-count":27,"URL":"https:\/\/doi.org\/10.1109\/pact.2013.6618819","relation":{},"subject":[],"published":{"date-parts":[[2013,10]]}}}