{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,12]],"date-time":"2025-06-12T22:02:34Z","timestamp":1749765754399},"reference-count":40,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,10]]},"DOI":"10.1109\/pact.2013.6618826","type":"proceedings-article","created":{"date-parts":[[2013,10,10]],"date-time":"2013-10-10T19:35:09Z","timestamp":1381433709000},"page":"375-386","source":"Crossref","is-referenced-by-count":4,"title":["Generating efficient data movement code for heterogeneous architectures with distributed-memory"],"prefix":"10.1109","author":[{"family":"Lei Fang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Peng Liu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Qi Hu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michael C.","family":"Huang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Guofan Jiang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"19","DOI":"10.1109\/2.55503"},{"key":"35","first-page":"24","article-title":"The SPLASH-2 programs: characterization and methodological considerations","author":"woo","year":"1995","journal-title":"Proceedings 22nd Annual International Symposium on Computer Architecture ISCA"},{"doi-asserted-by":"publisher","key":"17","DOI":"10.1145\/1454115.1454138"},{"doi-asserted-by":"publisher","key":"36","DOI":"10.1109\/71.139202"},{"doi-asserted-by":"publisher","key":"18","DOI":"10.1109\/PACT.2009.24"},{"year":"1992","author":"wallach","journal-title":"PHD A Hierarchical Cache Coherent Protocol","key":"33"},{"doi-asserted-by":"publisher","key":"15","DOI":"10.1007\/s11390-010-9321-5"},{"doi-asserted-by":"publisher","key":"34","DOI":"10.1145\/70082.68205"},{"key":"16","first-page":"312","article-title":"Reducing memory and traffic requirements for scalable directory-based cache coherence schemes","author":"gupta","year":"1990","journal-title":"Proceedings of the International Conference on Parallel Processing"},{"doi-asserted-by":"publisher","key":"39","DOI":"10.1145\/1854273.1854294"},{"doi-asserted-by":"publisher","key":"13","DOI":"10.1109\/MM.2010.31"},{"doi-asserted-by":"publisher","key":"14","DOI":"10.1145\/2000064.2000076"},{"doi-asserted-by":"publisher","key":"37","DOI":"10.1109\/MICRO.2007.14"},{"key":"11","first-page":"341","article-title":"Slid-a cost-effective and scalable limited-directory scheme for cache coherence","author":"chen","year":"1993","journal-title":"Proc Parallel Arch and Lang Europe"},{"doi-asserted-by":"publisher","key":"38","DOI":"10.1145\/1669112.1669166"},{"key":"12","first-page":"258","article-title":"Segment directory enhancing the limited directory cache coherence schemes","author":"choi","year":"1999","journal-title":"Proceedings of the International Parallel and Distributed Processing Symposium"},{"doi-asserted-by":"publisher","key":"21","DOI":"10.1109\/MM.2010.38"},{"doi-asserted-by":"publisher","key":"20","DOI":"10.1109\/DATE.2009.5090700"},{"doi-asserted-by":"publisher","key":"40","DOI":"10.1109\/PACT.2011.10"},{"doi-asserted-by":"publisher","key":"22","DOI":"10.1109\/ISCA.1997.604692"},{"doi-asserted-by":"publisher","key":"23","DOI":"10.1145\/379189.379198"},{"doi-asserted-by":"publisher","key":"24","DOI":"10.1145\/1250662.1250670"},{"key":"25","doi-asserted-by":"crossref","first-page":"234","DOI":"10.1145\/1080695.1069990","article-title":"Regionscout: Exploiting coarse grain sharing in snoop-based coherence","author":"moshovos","year":"2005","journal-title":"Proceedings of the International Symposium on Computer Architecture"},{"doi-asserted-by":"publisher","key":"26","DOI":"10.1145\/181181.181271"},{"doi-asserted-by":"publisher","key":"27","DOI":"10.1109\/SPDP.1992.242703"},{"doi-asserted-by":"publisher","key":"28","DOI":"10.1109\/ISCA.1990.134519"},{"doi-asserted-by":"publisher","key":"29","DOI":"10.1109\/HPCA.2012.6168950"},{"doi-asserted-by":"publisher","key":"3","DOI":"10.1109\/MICRO.2012.39"},{"doi-asserted-by":"publisher","key":"2","DOI":"10.1109\/ISCA.1988.5238"},{"key":"10","first-page":"172","article-title":"An efficient hybrid cache coherence protocol for shared memory multiprocessors","author":"chang","year":"1996","journal-title":"Proceedings of the International Conference on Parallel Processing"},{"doi-asserted-by":"publisher","key":"1","DOI":"10.1109\/HPCA.2001.903255"},{"key":"30","first-page":"22","article-title":"Ultrasparc T2: A highly-treaded, power-efficient, SPARC SOC","author":"shah","year":"2007","journal-title":"Proc Asian Solid-State Circuits Conf"},{"key":"7","doi-asserted-by":"crossref","first-page":"246","DOI":"10.1145\/1080695.1069991","article-title":"Improving multiprocessor performance with coarse-grain coherence tracking","author":"cantin","year":"2005","journal-title":"Proceedings of the International Symposium on Computer Architecture"},{"year":"1997","author":"burger","journal-title":"The SimpleScalar tool set version 2 0","key":"6"},{"key":"32","article-title":"Inside intel next generation nehalem microarchitecture","author":"singhal","year":"2008","journal-title":"Hot Chips"},{"key":"5","first-page":"83","article-title":"Wattch: a framework for architectural-level power analysis and optimizations","author":"brooks","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"year":"1992","author":"simoni","journal-title":"Cache Coherence Directories for Scalable Multiprocessors","key":"31"},{"doi-asserted-by":"publisher","key":"4","DOI":"10.1145\/1454115.1454128"},{"doi-asserted-by":"publisher","key":"9","DOI":"10.1145\/106972.106995"},{"doi-asserted-by":"publisher","key":"8","DOI":"10.1109\/TC.1978.1675013"}],"event":{"name":"22nd International Conference on Parallel Architectures and Compilation Techniques (PACT)","start":{"date-parts":[[2013,9,7]]},"location":"Edinburgh","end":{"date-parts":[[2013,9,11]]}},"container-title":["Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6603429\/6618788\/06618826.pdf?arnumber=6618826","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,21]],"date-time":"2017-06-21T19:30:14Z","timestamp":1498073414000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6618826\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,10]]},"references-count":40,"URL":"https:\/\/doi.org\/10.1109\/pact.2013.6618826","relation":{},"subject":[],"published":{"date-parts":[[2013,10]]}}}