{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T11:25:44Z","timestamp":1730287544596,"version":"3.28.0"},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,9]]},"DOI":"10.1109\/patmos.2013.6662149","type":"proceedings-article","created":{"date-parts":[[2013,11,27]],"date-time":"2013-11-27T21:56:40Z","timestamp":1385589400000},"page":"9-15","source":"Crossref","is-referenced-by-count":5,"title":["Ultra low-power standard cell design using planar bulk CMOS in subthreshold operation"],"prefix":"10.1109","author":[{"given":"Marc","family":"Pons","sequence":"first","affiliation":[]},{"given":"Jean-Luc","family":"Nagel","sequence":"additional","affiliation":[]},{"given":"Daniel","family":"Severac","sequence":"additional","affiliation":[]},{"given":"Marc","family":"Morgan","sequence":"additional","affiliation":[]},{"given":"Daniel","family":"Sigg","sequence":"additional","affiliation":[]},{"given":"Pierre-Francois","family":"Ruedi","sequence":"additional","affiliation":[]},{"given":"Christian","family":"Piguet","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"13","first-page":"197","article-title":"Energy optimization of subthreshold-voltage sensor network processors computer architecture 2005 isca '05","author":"nazhandali","year":"2005","journal-title":"Proceedings 32nd International on"},{"key":"11","first-page":"1","article-title":"The first quartz electronic watch proceedings of the 12th international workshop on integrated circuit design","author":"piguet","year":"2002","journal-title":"Power and Timing Modeling Optimization and Simulation"},{"key":"12","article-title":"The icyflexr processor family","author":"arm","year":"2008","journal-title":"CSEM Scientific and Technical Report"},{"journal-title":"UC Berkeley BSIM Group","year":"0","key":"3"},{"key":"2","first-page":"1","article-title":"A 40 nm dualwidth standard cell library for near\/sub-threshold operation Circuits and Systems I: Regular Papers","volume":"99","author":"zhou","year":"2012","journal-title":"IEEE Transactions on"},{"journal-title":"Mentor Graphics Questa Advanced Simulator","year":"0","key":"10"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228533"},{"journal-title":"Cadence Encounter RTL Compiler","year":"0","key":"7"},{"journal-title":"Cadence Virtuoso Liberate","year":"0","key":"6"},{"journal-title":"Nano-CMOS Design for Manufacturability Robust Circuit and Physical Design for Sub-65 nm Technology Nodes","year":"2009","author":"wong","key":"5"},{"journal-title":"Low-Power Low-Voltage Standard Cell Libraries with A Limited Number of Cells","year":"2001","author":"masgonty","key":"4"},{"journal-title":"Mentor Graphics Eldo Simulator","year":"0","key":"9"},{"journal-title":"Cadence SoC Encounter RTL-to-GDSII System","year":"0","key":"8"}],"event":{"name":"2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)","start":{"date-parts":[[2013,9,9]]},"location":"Karlsruhe, Germany","end":{"date-parts":[[2013,9,11]]}},"container-title":["2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6646388\/6662142\/06662149.pdf?arnumber=6662149","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,23]],"date-time":"2017-03-23T03:00:17Z","timestamp":1490238017000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6662149\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,9]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/patmos.2013.6662149","relation":{},"subject":[],"published":{"date-parts":[[2013,9]]}}}