{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T09:35:21Z","timestamp":1729676121284,"version":"3.28.0"},"reference-count":43,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,9]]},"DOI":"10.1109\/patmos.2014.6951864","type":"proceedings-article","created":{"date-parts":[[2014,11,25]],"date-time":"2014-11-25T17:43:28Z","timestamp":1416937408000},"page":"1-8","source":"Crossref","is-referenced-by-count":4,"title":["Convex optimization of resource allocation in asymmetric and heterogeneous SoC"],"prefix":"10.1109","author":[{"given":"Amir","family":"Morad","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Leonid","family":"Yavits","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ran","family":"Ginosar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"19","DOI":"10.1109\/3DIC.2013.6702346"},{"doi-asserted-by":"publisher","key":"35","DOI":"10.1109\/ISVLSI.2009.27"},{"key":"17","article-title":"Exploring the design space of future CMPs","author":"huh","year":"2001","journal-title":"PACT"},{"doi-asserted-by":"publisher","key":"36","DOI":"10.1109\/4.148323"},{"doi-asserted-by":"publisher","key":"18","DOI":"10.1109\/IEDM.2003.1269421"},{"year":"2013","author":"natarajan","journal-title":"Modeling Multi-threaded Programs Execution Time in the Many-core Era","key":"33"},{"year":"2008","author":"loh","journal-title":"The Cost of Uncore in Throughput-oriented Many-core Processors","key":"15"},{"year":"1994","author":"wilton","journal-title":"An enhanced access and cycle time model for on-chip caches","key":"34"},{"key":"16","first-page":"291","author":"hiriart-urruty","year":"1996","journal-title":"Convex Analysis and Minimization Algorithms Fundamentals"},{"key":"39","first-page":"37","article-title":"Application specific buffer allocation for wonnhole routing networks-on-chip","author":"liwei","year":"2008","journal-title":"Network-on- Chip Architectures"},{"year":"2010","author":"wentzlaff","journal-title":"Core Count Vs Cache Size for Manycore Architectures in the Cloud","key":"13"},{"year":"1999","author":"pollack","journal-title":"New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies","key":"14"},{"key":"37","article-title":"Perfonnance, power efficiency, and scalability of asymmetric cluster chip multiprocessors","volume":"4","author":"morad","year":"2005","journal-title":"IEEE Computer Architecture Letters"},{"doi-asserted-by":"publisher","key":"11","DOI":"10.1177\/109434209100500306"},{"key":"38","doi-asserted-by":"crossref","DOI":"10.1109\/L-CA.2012.3","article-title":"MultiAmdahl: How should T divide My heterogeneous chip?","author":"zidenberg","year":"2012","journal-title":"IEEE Computer Architecture Letters"},{"doi-asserted-by":"publisher","key":"12","DOI":"10.1109\/MC.2008.494"},{"key":"21","article-title":"Perfonnance, area, and bandwidth implications for large scale CMP cache design","author":"zhao","year":"2007","journal-title":"CMP-MSI"},{"doi-asserted-by":"publisher","key":"20","DOI":"10.1016\/j.parco.2013.11.001"},{"year":"2006","author":"guz","journal-title":"Nahalal Memory Organization for Chip Multiprocessors","key":"43"},{"doi-asserted-by":"publisher","key":"42","DOI":"10.1109\/DATE.2007.364517"},{"key":"41","first-page":"519","article-title":"Three-dimensional cache design exploration using 3DCacti","author":"tsai","year":"2005","journal-title":"ICCD"},{"key":"40","article-title":"Delay analysis of wonnhole based heterogeneous NOC","author":"ben-itzhak","year":"2011","journal-title":"Fifth IEEE\/ACM International Symposium on Networks on Chip"},{"doi-asserted-by":"publisher","key":"22","DOI":"10.1109\/MC.2008.209"},{"year":"2013","author":"grant","journal-title":"CVX Matlab software for disciplined convex programming version 2 0 beta","key":"23"},{"key":"24","doi-asserted-by":"crossref","first-page":"95","DOI":"10.1007\/978-1-84800-155-8_7","article-title":"Graph implementations for nonsmooth convex programs","author":"grant","year":"2008","journal-title":"Lecture Notes in Control and Information Sciences"},{"key":"25","article-title":"Navigo: An early-stage model to study power-constrained architectures and specialization","author":"hempstead","year":"2009","journal-title":"Workshop Model Benchmark Simulation (MoBS)"},{"year":"2012","journal-title":"MATLAB Optimization Toolbox Release","key":"26"},{"year":"2009","author":"muralimanohar","journal-title":"CACTI 6 0 A Tool to Understand Large Caches","key":"27"},{"doi-asserted-by":"publisher","key":"28","DOI":"10.1109\/MICRO.2007.33"},{"doi-asserted-by":"publisher","key":"29","DOI":"10.1137\/1035044"},{"doi-asserted-by":"publisher","key":"3","DOI":"10.1109\/TC.2011.169"},{"year":"2006","author":"alameldeen","journal-title":"Using Compression to Improve Chip Multiprocessor Perfonnance","key":"2"},{"doi-asserted-by":"publisher","key":"10","DOI":"10.1145\/1454115.1454128"},{"year":"2010","author":"agarwal","journal-title":"Core Count Vs Cache Size for Manycore Architectures in the Cloud","key":"1"},{"key":"30","first-page":"1","article-title":"Energy aware race to halt: A down to EARtH approach for platfonn energy management; A","volume":"pp","author":"rotem","year":"0","journal-title":"Computer Architecture Letters"},{"year":"2013","author":"morad","journal-title":"Optimization of Asvmmetric and Heterogeneous Multi Core","key":"7"},{"year":"2014","author":"morad","journal-title":"Convex Optimization of Resource Allocation in Asymmetric and Heterogeneous Multicore","key":"6"},{"doi-asserted-by":"publisher","key":"32","DOI":"10.1017\/CBO9780511804441"},{"key":"5","article-title":"Data sharing in multi-threaded applications and its impact on chip design","author":"krishna","year":"2012","journal-title":"ISPASS"},{"key":"31","first-page":"746","article-title":"Thousand core chips: A technology perspective","author":"borkar","year":"2007","journal-title":"Proc ACMliEEE 44th Design Automation Conl (DAC)"},{"doi-asserted-by":"publisher","key":"4","DOI":"10.1109\/TVLSI.2008.2000867"},{"doi-asserted-by":"publisher","key":"9","DOI":"10.1137\/1.9780898718829.ch5"},{"key":"8","article-title":"Generalized multi amdahl: Optimization of heterogeneous multi-accelerator SOC","author":"morad","year":"2012","journal-title":"IEEE Computer Architecture Letters"}],"event":{"name":"2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)","start":{"date-parts":[[2014,9,29]]},"location":"Palma de Mallorca, Spain","end":{"date-parts":[[2014,10,1]]}},"container-title":["2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6942524\/6951857\/06951864.pdf?arnumber=6951864","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,22]],"date-time":"2017-06-22T20:55:45Z","timestamp":1498164945000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6951864\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,9]]},"references-count":43,"URL":"https:\/\/doi.org\/10.1109\/patmos.2014.6951864","relation":{},"subject":[],"published":{"date-parts":[[2014,9]]}}}