{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T11:26:01Z","timestamp":1730287561320,"version":"3.28.0"},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,9]]},"DOI":"10.1109\/patmos.2014.6951903","type":"proceedings-article","created":{"date-parts":[[2014,11,25]],"date-time":"2014-11-25T22:43:28Z","timestamp":1416955408000},"page":"1-7","source":"Crossref","is-referenced-by-count":1,"title":["Estimating power consumption of multiple modular redundant designs in SRAM-based FPGAs for high dependable applications"],"prefix":"10.1109","author":[{"given":"Jimmy","family":"Tarrillo","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Fernanda Lima","family":"Kastensmidt","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"13","first-page":"1","volume":"202","year":"2010","journal-title":"Virtex-5 FPGA Data Sheet DC and Switching Characteristics Virtex-S FPGA Electrical Characteristics"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/RADECS.2013.6937377"},{"key":"12","first-page":"203","volume":"26","author":"kuon","year":"2007","journal-title":"Measuring the Gap between FPGAs and ASICs"},{"journal-title":"Hardware Configuration of Redundant Safety Integrated Systems","year":"2013","author":"williams","key":"3"},{"key":"2","article-title":"System hardening against upsets and real space applications","author":"pignol","year":"2013","journal-title":"Torrents 2013"},{"key":"1","first-page":"1","author":"instrument","year":"2008","journal-title":"Redundant System Basic Concepts"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1002\/047122460X"},{"key":"7","first-page":"1","volume":"864","author":"chapman","year":"2010","journal-title":"SEU strategies for Virtex-5 devices"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2005.853449"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2013.2246581"},{"key":"4","first-page":"147","article-title":"Xce1150 FPGA on mars","volume":"2","author":"story","year":"2010","journal-title":"Nat Chern"},{"key":"9","article-title":"A review of xilinx FPGA architectural reliability concerns from virtex to virtex-S","author":"quinn","year":"2007","journal-title":"Europ Conferen on Radiation and Effects on Componentes"},{"key":"8","volume":"100","author":"description","year":"2009","journal-title":"Summary of Virtex-S FPGA Features"}],"event":{"name":"2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)","start":{"date-parts":[[2014,9,29]]},"location":"Palma de Mallorca, Spain","end":{"date-parts":[[2014,10,1]]}},"container-title":["2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6942524\/6951857\/06951903.pdf?arnumber=6951903","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,24]],"date-time":"2017-03-24T05:17:38Z","timestamp":1490332658000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6951903\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,9]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/patmos.2014.6951903","relation":{},"subject":[],"published":{"date-parts":[[2014,9]]}}}