{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T21:07:40Z","timestamp":1729631260128,"version":"3.28.0"},"reference-count":28,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,9]]},"DOI":"10.1109\/patmos.2016.7833675","type":"proceedings-article","created":{"date-parts":[[2017,1,30]],"date-time":"2017-01-30T20:44:17Z","timestamp":1485809057000},"page":"120-127","source":"Crossref","is-referenced-by-count":1,"title":["Analysis of stress effects on timing of nano-scaled CMOS digital integrated circuits"],"prefix":"10.1109","author":[{"given":"Hossein","family":"Aghababa","sequence":"first","affiliation":[]},{"given":"Mohammadreza","family":"Kolahdouz","sequence":"additional","affiliation":[]},{"given":"Behjat","family":"Forouzandeh","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.1109\/IEDM.2005.1609388"},{"doi-asserted-by":"publisher","key":"ref11","DOI":"10.1145\/1353629.1353666"},{"doi-asserted-by":"publisher","key":"ref12","DOI":"10.1145\/1391469.1391700"},{"doi-asserted-by":"publisher","key":"ref13","DOI":"10.1109\/IEDM.2002.1175771"},{"doi-asserted-by":"publisher","key":"ref14","DOI":"10.1109\/TSM.2008.2010731"},{"doi-asserted-by":"publisher","key":"ref15","DOI":"10.1109\/ESSDER.2004.1356573"},{"key":"ref16","doi-asserted-by":"crossref","first-page":"123","DOI":"10.29292\/jics.v10i2.414","article-title":"Improving Analytical Delay Modeling for CMOS Inverters","volume":"10","author":"maranghello","year":"2015","journal-title":"Journal of Integrated Circuits and Systems"},{"doi-asserted-by":"publisher","key":"ref17","DOI":"10.1109\/TCSI.2013.2295028"},{"key":"ref18","article-title":"BSIM4.6.4 MOSFET model","author":"morshed","year":"2009","journal-title":"User's Manual Department of Electrical Engineering and Computer Sciences University of California"},{"key":"ref19","article-title":"Impact of layout on variability of devices for sub 90nm Technologies","author":"pramanik","year":"2006","journal-title":"IEEE Electron Devices Society Santa Clara Chapter Meeting"},{"doi-asserted-by":"publisher","key":"ref28","DOI":"10.1117\/12.793117"},{"key":"ref4","first-page":"269","article-title":"Impact of STI mechanical stress in highly scaled MOSFETs","author":"sheu","year":"2003","journal-title":"Proc Int Symp VLSI Technology Systems and Applications"},{"key":"ref27","first-page":"823","article-title":"Modeling and Analysis of Non-Rectangular Gate for Post-Lithography Circuit simulation","author":"singhal","year":"2007","journal-title":"Proc ACM\/IEEE Design Automation Conf"},{"doi-asserted-by":"publisher","key":"ref3","DOI":"10.1109\/VLSIT.2004.1345387"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.1109\/IEDM.2002.1175792"},{"doi-asserted-by":"publisher","key":"ref5","DOI":"10.1109\/ICCAD.2008.4681652"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1109\/ICCAD.2007.4397248"},{"doi-asserted-by":"publisher","key":"ref7","DOI":"10.1109\/TED.2005.881001"},{"key":"ref2","first-page":"176","article-title":"Experimental and comparative investigation of low and high field transport in substrate-and process-induced strained nanoscale MOSFETs","author":"andrieu","year":"2005","journal-title":"Proc VLSI Tech Symp Tech Dig"},{"doi-asserted-by":"publisher","key":"ref9","DOI":"10.1109\/IEDM.2004.1419385"},{"doi-asserted-by":"publisher","key":"ref1","DOI":"10.1109\/IEDM.1999.824277"},{"key":"ref20","article-title":"Improving design quality by managing process variability","author":"ma","year":"2009","journal-title":"presented at International Symp on Quality Electronic Design"},{"doi-asserted-by":"publisher","key":"ref22","DOI":"10.1109\/VLSIT.2007.4339693"},{"year":"2005","journal-title":"HSPICE Device Models Quick Reference Guide","key":"ref21"},{"doi-asserted-by":"publisher","key":"ref24","DOI":"10.1109\/43.920682"},{"key":"ref23","first-page":"61","article-title":"Robust analytical gate delay modeling for low voltage circuits","author":"ramalingam","year":"2006","journal-title":"Proc Asia and South Pacific Design Automation Conference"},{"key":"ref26","first-page":"286","article-title":"A New Method to Improve Accuracy of Leakage Current Estimation for Transistors with Non-rectangular Gates due to Sub-wavelength Lithography Effects","author":"tsai","year":"2008","journal-title":"Proc IEEE\/ACM Conf Computer-Aided Design"},{"doi-asserted-by":"publisher","key":"ref25","DOI":"10.1109\/4.52187"}],"event":{"name":"2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)","start":{"date-parts":[[2016,9,21]]},"location":"Bremen, Germany","end":{"date-parts":[[2016,9,23]]}},"container-title":["2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7813533\/7833417\/07833675.pdf?arnumber=7833675","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,23]],"date-time":"2022-07-23T01:46:24Z","timestamp":1658540784000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7833675\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,9]]},"references-count":28,"URL":"https:\/\/doi.org\/10.1109\/patmos.2016.7833675","relation":{},"subject":[],"published":{"date-parts":[[2016,9]]}}}